c23b4fbdbb
Now that #149310 has restricted lifetime intrinsics to only work on allocas, we can also drop the explicit size argument. Instead, the size is implied by the alloca. This removes the ability to only mark a prefix of an alloca alive/dead. We never used that capability, so we should remove the need to handle that possibility everywhere (though many key places, including stack coloring, did not actually respect this).
127 lines
4.3 KiB
LLVM
127 lines
4.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -passes="partial-inliner" -skip-partial-inlining-cost-analysis -S < %s | FileCheck %s
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; RUN: opt -passes=partial-inliner -skip-partial-inlining-cost-analysis -S < %s | FileCheck %s
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define dso_local signext i32 @callee(i32 signext %c1, i32 signext %c2) !prof !30 {
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; CHECK-LABEL: @callee(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[RC:%.*]] = alloca i32, align 4
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; CHECK-NEXT: store i32 0, ptr [[RC]], align 4
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; CHECK-NEXT: switch i32 [[C1:%.*]], label [[SW_DEFAULT:%.*]] [
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; CHECK-NEXT: i32 0, label [[SW_BB:%.*]]
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; CHECK-NEXT: i32 1, label [[SW_BB1:%.*]]
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; CHECK-NEXT: i32 2, label [[SW_BB2:%.*]]
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; CHECK-NEXT: ], !prof !31
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; CHECK: sw.bb:
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; CHECK-NEXT: store i32 1, ptr [[RC]], align 4
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; CHECK-NEXT: br label [[SW_EPILOG:%.*]]
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; CHECK: sw.bb1:
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; CHECK-NEXT: store i32 2, ptr [[RC]], align 4
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; CHECK-NEXT: br label [[SW_EPILOG]]
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; CHECK: sw.bb2:
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; CHECK-NEXT: store i32 4, ptr [[RC]], align 4
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; CHECK-NEXT: br label [[SW_EPILOG]]
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; CHECK: sw.default:
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; CHECK-NEXT: store i32 [[C2:%.*]], ptr [[RC]], align 4
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; CHECK-NEXT: br label [[SW_EPILOG]]
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; CHECK: sw.epilog:
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; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[RC]], align 4
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; CHECK-NEXT: ret i32 [[TMP0]]
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;
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entry:
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%rc = alloca i32, align 4
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store i32 0, ptr %rc, align 4
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switch i32 %c1, label %sw.default [
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i32 0, label %sw.bb
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i32 1, label %sw.bb1
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i32 2, label %sw.bb2
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], !prof !31
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sw.bb: ;; cold
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store i32 1, ptr %rc, align 4
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br label %sw.epilog
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sw.bb1:
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store i32 2, ptr %rc, align 4
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br label %sw.epilog
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sw.bb2: ;; cold
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store i32 4, ptr %rc, align 4
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br label %sw.epilog
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sw.default:
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store i32 %c2, ptr %rc, align 4
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br label %sw.epilog
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sw.epilog:
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%0 = load i32, ptr %rc, align 4
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ret i32 %0
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}
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define dso_local signext i32 @caller(i32 signext %c) !prof !30 {
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; CHECK-LABEL: @caller(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[RC_I:%.*]] = alloca i32, align 4
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; CHECK-NEXT: call void @llvm.lifetime.start.p0(ptr [[RC_I]])
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; CHECK-NEXT: store i32 0, ptr [[RC_I]], align 4
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; CHECK-NEXT: switch i32 [[C:%.*]], label [[SW_DEFAULT_I:%.*]] [
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; CHECK-NEXT: i32 0, label [[CODEREPL_I:%.*]]
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; CHECK-NEXT: i32 1, label [[SW_BB1_I:%.*]]
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; CHECK-NEXT: i32 2, label [[CODEREPL1_I:%.*]]
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; CHECK-NEXT: ], !prof !31
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; CHECK: codeRepl.i:
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; CHECK-NEXT: call void @callee.1.sw.bb(ptr [[RC_I]])
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; CHECK-NEXT: br label [[CALLEE_1_EXIT:%.*]]
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; CHECK: sw.bb1.i:
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; CHECK-NEXT: store i32 2, ptr [[RC_I]], align 4
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; CHECK-NEXT: br label [[CALLEE_1_EXIT]]
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; CHECK: codeRepl1.i:
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; CHECK-NEXT: call void @callee.1.sw.bb2(ptr [[RC_I]])
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; CHECK-NEXT: br label [[CALLEE_1_EXIT]]
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; CHECK: sw.default.i:
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; CHECK-NEXT: store i32 [[C]], ptr [[RC_I]], align 4
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; CHECK-NEXT: br label [[CALLEE_1_EXIT]]
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; CHECK: callee.1.exit:
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; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[RC_I]], align 4
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; CHECK-NEXT: call void @llvm.lifetime.end.p0(ptr [[RC_I]])
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;
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entry:
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%0 = call signext i32 @callee(i32 signext %c, i32 signext %c)
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ret i32 %0
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}
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!llvm.module.flags = !{!0, !1}
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!0 = !{i32 1, !"wchar_size", i32 4}
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!1 = !{i32 1, !"ProfileSummary", !2}
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!2 = !{!3, !4, !5, !6, !7, !8, !9, !10, !11, !12}
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!3 = !{!"ProfileFormat", !"InstrProf"}
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!4 = !{!"TotalCount", i64 2}
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!5 = !{!"MaxCount", i64 1000}
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!6 = !{!"MaxInternalCount", i64 1000}
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!7 = !{!"MaxFunctionCount", i64 1000}
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!8 = !{!"NumCounts", i64 4}
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!9 = !{!"NumFunctions", i64 2}
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!10 = !{!"IsPartialProfile", i64 0}
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!11 = !{!"PartialProfileRatio", double 0.000000e+00}
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!12 = !{!"DetailedSummary", !13}
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!13 = !{!14, !15, !16, !17, !18, !19, !20, !21, !22, !23, !24, !25, !26, !27, !28, !29}
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!14 = !{i32 10000, i64 0, i32 0}
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!15 = !{i32 100000, i64 0, i32 0}
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!16 = !{i32 200000, i64 0, i32 0}
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!17 = !{i32 300000, i64 0, i32 0}
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!18 = !{i32 400000, i64 0, i32 0}
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!19 = !{i32 500000, i64 1, i32 2}
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!20 = !{i32 600000, i64 1, i32 2}
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!21 = !{i32 700000, i64 1, i32 2}
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!22 = !{i32 800000, i64 1, i32 2}
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!23 = !{i32 900000, i64 1, i32 2}
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!24 = !{i32 950000, i64 1, i32 2}
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!25 = !{i32 990000, i64 1, i32 2}
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!26 = !{i32 999000, i64 1, i32 2}
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!27 = !{i32 999900, i64 1, i32 2}
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!28 = !{i32 999990, i64 1, i32 2}
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!29 = !{i32 999999, i64 1, i32 2}
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!30 = !{!"function_entry_count", i64 1000}
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!31 = !{!"branch_weights", i32 500, i32 10, i32 150, i32 40}
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