717899ce86
This PR adds support for loading bit-field members from structs using the `get_bitfield` operation. It enables retrieving the address of the bitfield-packed member but does **not** yet support volatile bitfields this will be addressed in a future PR.
61 lines
2.4 KiB
C++
61 lines
2.4 KiB
C++
// RUN: %clang_cc1 -std=c++17 -triple x86_64-unknown-linux-gnu -fclangir -emit-cir %s -o %t.cir
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// RUN: FileCheck --input-file=%t.cir %s --check-prefix=CIR
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// RUN: %clang_cc1 -std=c++17 -triple x86_64-unknown-linux-gnu -fclangir -emit-llvm %s -o %t-cir.ll
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// RUN: FileCheck --input-file=%t-cir.ll %s --check-prefix=LLVM
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// RUN: %clang_cc1 -std=c++17 -triple x86_64-unknown-linux-gnu -emit-llvm %s -o %t.ll
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// RUN: FileCheck --input-file=%t.ll %s --check-prefix=OGCG
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typedef struct {
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int a : 4;
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int b : 27;
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int c : 17;
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int d : 2;
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int e : 15;
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unsigned f; // type other than int above, not a bitfield
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} S;
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// CIR-DAG: !rec_S = !cir.record<struct "S" {!u64i, !u16i, !u32i}>
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// CIR-DAG: #bfi_c = #cir.bitfield_info<name = "c", storageType = !u64i, size = 17, offset = 32, isSigned = true>
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// LLVM-DAG: %struct.S = type { i64, i16, i32 }
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// OGCG-DAG: %struct.S = type { i64, i16, i32 }
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typedef struct {
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int a : 3; // one bitfield with size < 8
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unsigned b;
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} T;
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// CIR-DAG: !rec_T = !cir.record<struct "T" {!u8i, !u32i}>
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// LLVM-DAG: %struct.T = type { i8, i32 }
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// OGCG-DAG: %struct.T = type { i8, i32 }
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void def() {
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S s;
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T t;
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}
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int load_field(S* s) {
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return s->c;
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}
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// CIR: cir.func dso_local @_Z10load_field
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// CIR: [[TMP0:%.*]] = cir.alloca !cir.ptr<!rec_S>, !cir.ptr<!cir.ptr<!rec_S>>, ["s", init]
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// CIR: [[TMP1:%.*]] = cir.load{{.*}} [[TMP0]] : !cir.ptr<!cir.ptr<!rec_S>>, !cir.ptr<!rec_S>
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// CIR: [[TMP2:%.*]] = cir.get_member [[TMP1]][0] {name = "c"} : !cir.ptr<!rec_S> -> !cir.ptr<!u64i>
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// CIR: [[TMP3:%.*]] = cir.get_bitfield(#bfi_c, [[TMP2]] : !cir.ptr<!u64i>) -> !s32i
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// LLVM: define dso_local i32 @_Z10load_fieldP1S
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// LLVM: [[TMP0:%.*]] = alloca ptr, i64 1, align 8
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// LLVM: [[TMP1:%.*]] = alloca i32, i64 1, align 4
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// LLVM: [[TMP2:%.*]] = load ptr, ptr [[TMP0]], align 8
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// LLVM: [[TMP3:%.*]] = getelementptr %struct.S, ptr [[TMP2]], i32 0, i32 0
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// LLVM: [[TMP4:%.*]] = load i64, ptr [[TMP3]], align 8
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// LLVM: [[TMP5:%.*]] = shl i64 [[TMP4]], 15
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// LLVM: [[TMP6:%.*]] = ashr i64 [[TMP5]], 47
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// LLVM: [[TMP7:%.*]] = trunc i64 [[TMP6]] to i32
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// OGCG: define dso_local noundef i32 @_Z10load_fieldP1S
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// OGCG: [[TMP0:%.*]] = alloca ptr, align 8
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// OGCG: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8
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// OGCG: [[TMP2:%.*]] = load i64, ptr [[TMP1]], align 4
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// OGCG: [[TMP3:%.*]] = shl i64 [[TMP2]], 15
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// OGCG: [[TMP4:%.*]] = ashr i64 [[TMP3]], 47
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// OGCG: [[TMP5:%.*]] = trunc i64 [[TMP4]] to i32
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