c3536b263f
This defines some new target features. These are subsets of existing features that reflect implementation concerns: - "call-indirect-overlong" - implied by "reference-types"; just the overlong encoding for the `call_indirect` immediate, and not the actual reference types. - "bulk-memory-opt" - implied by "bulk-memory": just `memory.copy` and `memory.fill`, and not the other instructions in the bulk-memory proposal. This is split out from https://github.com/llvm/llvm-project/pull/112035. --------- Co-authored-by: Heejin Ahn <aheejin@gmail.com>
79 lines
2.6 KiB
C++
79 lines
2.6 KiB
C++
//===-- WebAssemblySubtarget.cpp - WebAssembly Subtarget Information ------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This file implements the WebAssembly-specific subclass of
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/// TargetSubtarget.
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///
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//===----------------------------------------------------------------------===//
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#include "WebAssemblySubtarget.h"
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#include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
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#include "WebAssemblyInstrInfo.h"
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#include "llvm/MC/TargetRegistry.h"
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using namespace llvm;
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#define DEBUG_TYPE "wasm-subtarget"
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#define GET_SUBTARGETINFO_CTOR
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#define GET_SUBTARGETINFO_TARGET_DESC
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#include "WebAssemblyGenSubtargetInfo.inc"
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WebAssemblySubtarget &
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WebAssemblySubtarget::initializeSubtargetDependencies(StringRef CPU,
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StringRef FS) {
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// Determine default and user-specified characteristics
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LLVM_DEBUG(llvm::dbgs() << "initializeSubtargetDependencies\n");
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if (CPU.empty())
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CPU = "generic";
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ParseSubtargetFeatures(CPU, /*TuneCPU*/ CPU, FS);
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FeatureBitset Bits = getFeatureBits();
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// bulk-memory implies bulk-memory-opt
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if (HasBulkMemory) {
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HasBulkMemoryOpt = true;
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Bits.set(WebAssembly::FeatureBulkMemoryOpt);
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}
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// reference-types implies call-indirect-overlong
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if (HasReferenceTypes) {
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HasCallIndirectOverlong = true;
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Bits.set(WebAssembly::FeatureCallIndirectOverlong);
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}
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// In case we changed any bits, update `MCSubtargetInfo`'s `FeatureBitset`.
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setFeatureBits(Bits);
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return *this;
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}
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WebAssemblySubtarget::WebAssemblySubtarget(const Triple &TT,
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const std::string &CPU,
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const std::string &FS,
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const TargetMachine &TM)
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: WebAssemblyGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS),
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TargetTriple(TT), InstrInfo(initializeSubtargetDependencies(CPU, FS)),
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TLInfo(TM, *this) {}
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bool WebAssemblySubtarget::enableAtomicExpand() const {
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// If atomics are disabled, atomic ops are lowered instead of expanded
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return hasAtomics();
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}
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bool WebAssemblySubtarget::enableMachineScheduler() const {
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// Disable the MachineScheduler for now. Even with ShouldTrackPressure set and
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// enableMachineSchedDefaultSched overridden, it appears to have an overall
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// negative effect for the kinds of register optimizations we're doing.
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return false;
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}
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bool WebAssemblySubtarget::useAA() const { return true; }
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