11ab23c33d
Both conceptually belong to the same subtarget, so it should not be necessary to pass in the context TargetRegisterInfo to any TargetInstrInfo member. Add this reference so those superfluous arguments can be removed. Most targets placed their TargetRegisterInfo as a member in TargetInstrInfo. A few had this owned by the TargetSubtargetInfo, so unify all targets to look the same.
236 lines
8.4 KiB
C++
236 lines
8.4 KiB
C++
//===-- WebAssemblyInstrInfo.cpp - WebAssembly Instruction Information ----===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This file contains the WebAssembly implementation of the
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/// TargetInstrInfo class.
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///
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//===----------------------------------------------------------------------===//
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#include "WebAssemblyInstrInfo.h"
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#include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
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#include "WebAssembly.h"
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#include "WebAssemblyMachineFunctionInfo.h"
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#include "WebAssemblySubtarget.h"
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#include "WebAssemblyUtilities.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineMemOperand.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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using namespace llvm;
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#define DEBUG_TYPE "wasm-instr-info"
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#define GET_INSTRINFO_CTOR_DTOR
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#include "WebAssemblyGenInstrInfo.inc"
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// defines WebAssembly::getNamedOperandIdx
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#define GET_INSTRINFO_NAMED_OPS
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#include "WebAssemblyGenInstrInfo.inc"
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WebAssemblyInstrInfo::WebAssemblyInstrInfo(const WebAssemblySubtarget &STI)
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: WebAssemblyGenInstrInfo(STI, RI, WebAssembly::ADJCALLSTACKDOWN,
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WebAssembly::ADJCALLSTACKUP,
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WebAssembly::CATCHRET),
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RI(STI.getTargetTriple()) {}
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bool WebAssemblyInstrInfo::isReMaterializableImpl(
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const MachineInstr &MI) const {
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switch (MI.getOpcode()) {
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case WebAssembly::CONST_I32:
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case WebAssembly::CONST_I64:
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case WebAssembly::CONST_F32:
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case WebAssembly::CONST_F64:
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// TargetInstrInfo::isReMaterializableImpl misses these
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// because of the ARGUMENTS implicit def, so we manualy override it here.
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return true;
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default:
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return TargetInstrInfo::isReMaterializableImpl(MI);
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}
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}
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void WebAssemblyInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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const DebugLoc &DL, Register DestReg,
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Register SrcReg, bool KillSrc,
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bool RenamableDest,
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bool RenamableSrc) const {
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// This method is called by post-RA expansion, which expects only pregs to
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// exist. However we need to handle both here.
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auto &MRI = MBB.getParent()->getRegInfo();
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const TargetRegisterClass *RC =
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DestReg.isVirtual()
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? MRI.getRegClass(DestReg)
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: MRI.getTargetRegisterInfo()->getMinimalPhysRegClass(DestReg);
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unsigned CopyOpcode = WebAssembly::getCopyOpcodeForRegClass(RC);
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BuildMI(MBB, I, DL, get(CopyOpcode), DestReg)
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.addReg(SrcReg, KillSrc ? RegState::Kill : 0);
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}
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MachineInstr *WebAssemblyInstrInfo::commuteInstructionImpl(
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MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const {
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// If the operands are stackified, we can't reorder them.
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WebAssemblyFunctionInfo &MFI =
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*MI.getParent()->getParent()->getInfo<WebAssemblyFunctionInfo>();
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if (MFI.isVRegStackified(MI.getOperand(OpIdx1).getReg()) ||
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MFI.isVRegStackified(MI.getOperand(OpIdx2).getReg()))
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return nullptr;
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// Otherwise use the default implementation.
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return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
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}
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// Branch analysis.
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bool WebAssemblyInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
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MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool /*AllowModify*/) const {
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const auto &MFI = *MBB.getParent()->getInfo<WebAssemblyFunctionInfo>();
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// WebAssembly has control flow that doesn't have explicit branches or direct
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// fallthrough (e.g. try/catch), which can't be modeled by analyzeBranch. It
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// is created after CFGStackify.
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if (MFI.isCFGStackified())
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return true;
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bool HaveCond = false;
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for (MachineInstr &MI : MBB.terminators()) {
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switch (MI.getOpcode()) {
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default:
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// Unhandled instruction; bail out.
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return true;
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case WebAssembly::BR_IF:
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if (HaveCond)
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return true;
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Cond.push_back(MachineOperand::CreateImm(true));
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Cond.push_back(MI.getOperand(1));
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TBB = MI.getOperand(0).getMBB();
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HaveCond = true;
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break;
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case WebAssembly::BR_UNLESS:
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if (HaveCond)
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return true;
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Cond.push_back(MachineOperand::CreateImm(false));
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Cond.push_back(MI.getOperand(1));
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TBB = MI.getOperand(0).getMBB();
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HaveCond = true;
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break;
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case WebAssembly::BR:
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if (!HaveCond)
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TBB = MI.getOperand(0).getMBB();
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else
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FBB = MI.getOperand(0).getMBB();
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break;
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}
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if (MI.isBarrier())
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break;
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}
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return false;
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}
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unsigned WebAssemblyInstrInfo::removeBranch(MachineBasicBlock &MBB,
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int *BytesRemoved) const {
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assert(!BytesRemoved && "code size not handled");
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MachineBasicBlock::instr_iterator I = MBB.instr_end();
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unsigned Count = 0;
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while (I != MBB.instr_begin()) {
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--I;
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if (I->isDebugInstr())
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continue;
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if (!I->isTerminator())
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break;
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// Remove the branch.
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I->eraseFromParent();
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I = MBB.instr_end();
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++Count;
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}
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return Count;
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}
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unsigned WebAssemblyInstrInfo::insertBranch(
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MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
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ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const {
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assert(!BytesAdded && "code size not handled");
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if (Cond.empty()) {
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if (!TBB)
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return 0;
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BuildMI(&MBB, DL, get(WebAssembly::BR)).addMBB(TBB);
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return 1;
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}
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assert(Cond.size() == 2 && "Expected a flag and a successor block");
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if (Cond[0].getImm())
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BuildMI(&MBB, DL, get(WebAssembly::BR_IF)).addMBB(TBB).add(Cond[1]);
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else
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BuildMI(&MBB, DL, get(WebAssembly::BR_UNLESS)).addMBB(TBB).add(Cond[1]);
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if (!FBB)
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return 1;
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BuildMI(&MBB, DL, get(WebAssembly::BR)).addMBB(FBB);
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return 2;
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}
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bool WebAssemblyInstrInfo::reverseBranchCondition(
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SmallVectorImpl<MachineOperand> &Cond) const {
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assert(Cond.size() == 2 && "Expected a flag and a condition expression");
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Cond.front() = MachineOperand::CreateImm(!Cond.front().getImm());
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return false;
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}
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ArrayRef<std::pair<int, const char *>>
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WebAssemblyInstrInfo::getSerializableTargetIndices() const {
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static const std::pair<int, const char *> TargetIndices[] = {
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{WebAssembly::TI_LOCAL, "wasm-local"},
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{WebAssembly::TI_GLOBAL_FIXED, "wasm-global-fixed"},
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{WebAssembly::TI_OPERAND_STACK, "wasm-operand-stack"},
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{WebAssembly::TI_GLOBAL_RELOC, "wasm-global-reloc"},
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{WebAssembly::TI_LOCAL_INDIRECT, "wasm-local-indirect"}};
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return ArrayRef(TargetIndices);
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}
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const MachineOperand &
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WebAssemblyInstrInfo::getCalleeOperand(const MachineInstr &MI) const {
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return WebAssembly::getCalleeOp(MI);
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}
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// This returns true when the instruction defines a value of a TargetIndex
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// operand that can be tracked by offsets. For Wasm, this returns true for only
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// local.set/local.tees. This is currently used by LiveDebugValues analysis.
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//
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// These are not included:
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// - In theory we need to add global.set here too, but we don't have global
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// indices at this point because they are relocatable and we address them by
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// names until linking, so we don't have 'offsets' (which are used to store
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// local/global indices) to deal with in LiveDebugValues. And we don't
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// associate debug info in values in globals anyway.
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// - All other value-producing instructions, i.e. instructions with defs, can
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// define values in the Wasm stack, which is represented by TI_OPERAND_STACK
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// TargetIndex. But they don't have offset info within the instruction itself,
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// and debug info analysis for them is handled separately in
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// WebAssemblyDebugFixup pass, so we don't worry about them here.
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bool WebAssemblyInstrInfo::isExplicitTargetIndexDef(const MachineInstr &MI,
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int &Index,
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int64_t &Offset) const {
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unsigned Opc = MI.getOpcode();
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if (WebAssembly::isLocalSet(Opc) || WebAssembly::isLocalTee(Opc)) {
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Index = WebAssembly::TI_LOCAL;
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Offset = MI.explicit_uses().begin()->getImm();
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return true;
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}
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return false;
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}
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