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llvm-project/llvm/lib/Target/RISCV
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Sam Elliott 6309cd8668
Revert "[NFC][MI] Tidy Up RegState enum use (1/2)" (#176190) 
Reverts llvm/llvm-project#176091

Reverting because some compilers were erroring on the call to
`Reg.isReg()` (which is not `constexpr`) in a `constexpr` function.
2026-01-15 07:58:05 -08:00
..
AsmParser
[RISCV] AI Foundry ET extensions for RISC-V (#174571)
2026-01-13 12:54:11 -08:00
Disassembler
[RISCV] AI Foundry ET extensions for RISC-V (#174571)
2026-01-13 12:54:11 -08:00
GISel
[RISCV][GISel] Support select vsetvli intrinsics (#174076)
2026-01-02 11:49:35 +08:00
MCA
[RISCVInsertVSETVLI] Don't allow getSEW/getLMUL to be called for hasSEWLMULRatioOnly(). NFC (#171554)
2025-12-09 22:06:15 -08:00
MCTargetDesc
[RISCV] AI Foundry ET extensions for RISC-V (#174571)
2026-01-13 12:54:11 -08:00
TargetInfo
[RISCV] Add initial assembler/MC layer support for big-endian (#146534)
2025-08-22 09:21:10 +02:00
CMakeLists.txt
[RISCV][NFC] Add RISCVVSETVLIInfoAnalysis
2026-01-12 12:00:55 +08:00
RISCV.h
[llvm][RISCV] Implement Zilsd load/store pair optimization (#158640)
2025-11-21 05:04:05 +00:00
RISCV.td
CodeGen: Make all targets override pseudos with pointers (#159881)
2025-11-26 14:57:14 +00:00
RISCVAsmPrinter.cpp
[RISC-V] Ensure MCTargetStreamer is initialized. (#174800)
2026-01-08 01:24:51 +00:00
RISCVCallingConv.cpp
[CodeGen] Provide original IR type to CC lowering (NFC) (#152709)
2025-08-11 08:57:53 +02:00
RISCVCallingConv.h
[CodeGen] Provide original IR type to CC lowering (NFC) (#152709)
2025-08-11 08:57:53 +02:00
RISCVCallingConv.td
[RISCV] Support PreserveMost calling convention (#148214)
2025-07-30 16:30:48 +08:00
RISCVCodeGenPrepare.cpp
[RISCV] Remove last use of @llvm.experimental.vp.splat in RISCVCodeGenPrepare. NFCI (#170543)
2025-12-08 06:09:03 +00:00
RISCVCombine.td
[RISCV][GISel] Fold G_FCONSTANT 0.0 store into G_CONSTANT x0 (#163008)
2025-10-23 15:50:04 +08:00
RISCVConstantPoolValue.cpp
…
RISCVConstantPoolValue.h
[Target] Add "override" where appropriate (NFC) (#165083)
2025-10-25 06:23:43 -07:00
RISCVDeadRegisterDefinitions.cpp
CodeGen: Remove TRI argument from getRegClass (#158225)
2025-11-10 15:43:55 -08:00
RISCVExpandAtomicPseudoInsts.cpp
[RISCV] 'Zalrsc' may permit non-base instructions (#165042)
2025-10-28 12:51:11 -07:00
RISCVExpandPseudoInsts.cpp
[RISCV] Add short forward branch support for qc.e.lb(u), qc.e.lh(u) and qc.e.lw (#172629)
2025-12-18 09:38:31 +05:30
RISCVFeatures.td
[RISCV] AI Foundry ET extensions for RISC-V (#174571)
2026-01-13 12:54:11 -08:00
RISCVFoldMemOffset.cpp
…
RISCVFrameLowering.cpp
[CodeGen][InlineSpiller] Add SubReg argument to loadRegFromStackSlot for subreg-reload (#175581)
2026-01-13 08:21:58 +05:30
RISCVFrameLowering.h
[CodeGen] Replace (Min,Max)CSFrameIndex with flag on frame object [NFCI] (#170905)
2025-12-06 14:00:55 -08:00
RISCVGatherScatterLowering.cpp
[IR] Replace alignment argument with attribute on masked intrinsics (#163802)
2025-10-20 08:50:09 +00:00
RISCVGISel.td
[RISCV][NFC] Simplify Imm range checks (#170497)
2025-12-04 06:04:49 +01:00
RISCVIndirectBranchTracking.cpp
[RISCV] Emit lpad for function with returns-twice attribute (#170520)
2025-12-04 13:25:57 +08:00
RISCVInsertReadWriteCSR.cpp
…
RISCVInsertVSETVLI.cpp
[RISCV][NFC] Add RISCVVSETVLIInfoAnalysis
2026-01-12 12:00:55 +08:00
RISCVInsertWriteVXRM.cpp
[llvm] Use "= default" (NFC) (#166088)
2025-11-02 17:16:47 -08:00
RISCVInstrFormats.td
[RISCV] AI Foundry ET extensions for RISC-V (#174571)
2026-01-13 12:54:11 -08:00
RISCVInstrFormatsC.td
[RISCV] Remove post-decoding instruction adjustments (#156360)
2025-09-04 16:02:34 +00:00
RISCVInstrFormatsV.td
…
RISCVInstrFormatsXAIF.td
[RISCV] AI Foundry ET extensions for RISC-V (#174571)
2026-01-13 12:54:11 -08:00
RISCVInstrGISel.td
…
RISCVInstrInfo.cpp
Revert "[NFC][MI] Tidy Up RegState enum use (1/2)" (#176190)
2026-01-15 07:58:05 -08:00
RISCVInstrInfo.h
[CodeGen][InlineSpiller] Add SubReg argument to loadRegFromStackSlot for subreg-reload (#175581)
2026-01-13 08:21:58 +05:30
RISCVInstrInfo.td
[RISCV][NFC] Push riscv_selectcc PatFrag Inwards (#175902)
2026-01-14 10:22:47 -08:00
RISCVInstrInfoA.td
[RISCV] Use GPR instead of ixlenimm for sextshamt in PseudoMaskedAMOMinMax. NFC (#171736)
2025-12-10 20:43:46 -08:00
RISCVInstrInfoC.td
[TableGen][DecoderEmitter][RISCV] Always handle bits<0> (#159951)
2025-09-22 20:50:17 +03:00
RISCVInstrInfoD.td
[RISCV] Enable rematerialization for scalar loads (#166774)
2025-11-24 18:14:19 +08:00
RISCVInstrInfoF.td
[RISCV] Use frmarg instead of ixlenimm in PseudoFROUND. NFC (#171563)
2025-12-09 22:05:44 -08:00
RISCVInstrInfoM.td
[RISCV][NFC] Cleanup Negative Predicate Names (#155017)
2025-08-22 14:46:41 -07:00
RISCVInstrInfoP.td
[RISCV][llvm] Support vselect codegen for P extension (#175744)
2026-01-14 14:02:55 +08:00
RISCVInstrInfoQ.td
…
RISCVInstrInfoSFB.td
[RISCV][NFC] Push riscv_selectcc PatFrag Inwards (#175902)
2026-01-14 10:22:47 -08:00
RISCVInstrInfoV.td
[RISCV] Add an OperandType to VMaskOp. NFC (#171926)
2025-12-11 20:03:47 -08:00
RISCVInstrInfoVPseudos.td
[RISCV] Add the missing SEW search table field to vector FMA instructions (#175646)
2026-01-12 17:24:57 -08:00
RISCVInstrInfoVSDPatterns.td
[llvm][RISCV] Support fma codegen for zvfbfa (#172949)
2026-01-05 16:22:48 +08:00
RISCVInstrInfoVVLPatterns.td
[RISCV][llvm] Support IS_FPCLASS codegen for zvfbfa (#175758)
2026-01-14 14:02:17 +08:00
RISCVInstrInfoXAIF.td
[RISCV] AI Foundry ET extensions for RISC-V (#174571)
2026-01-13 12:54:11 -08:00
RISCVInstrInfoXAndes.td
[RISCV][NFC] Push riscv_selectcc PatFrag Inwards (#175902)
2026-01-14 10:22:47 -08:00
RISCVInstrInfoXCV.td
[RISCV][NFC] Push riscv_selectcc PatFrag Inwards (#175902)
2026-01-14 10:22:47 -08:00
RISCVInstrInfoXMips.td
[RISCV] Add "MIPS" to name of MIPS-specific RISCVSubtarget functions. NFC (#162122)
2025-10-06 11:33:20 -07:00
RISCVInstrInfoXqccmp.td
…
RISCVInstrInfoXqci.td
[RISCV][NFC] Push riscv_selectcc PatFrag Inwards (#175902)
2026-01-14 10:22:47 -08:00
RISCVInstrInfoXRivos.td
[RISCV] Use sew and vec_policy for Rivos vector instruction operands. (#171721)
2025-12-10 17:46:10 -08:00
RISCVInstrInfoXSf.td
[RISCV] Add OperandType to tsimm5 used by Xsfvcp. (#171964)
2025-12-11 22:02:08 -08:00
RISCVInstrInfoXSfmm.td
[RISCV] Use vec_rm for VPseudoSF_MatMul_FRM. (#171573)
2025-12-10 13:14:46 -08:00
RISCVInstrInfoXSpacemiT.td
[RISCV] Fold argstr into class for XSMTVDot instructions. NFC.
2025-08-21 13:12:46 +08:00
RISCVInstrInfoXTHead.td
[RISCV] Use TargetConstant for the immediate RISCVISD::SHL_ADD nodes. (#166312)
2025-11-04 09:56:59 -08:00
RISCVInstrInfoXVentana.td
…
RISCVInstrInfoXwch.td
[RISCV] Remove post-decoding instruction adjustments (#156360)
2025-09-04 16:02:34 +00:00
RISCVInstrInfoZa.td
[RISCV] Reorder ins/outs of atomic instruction to match their assembly order. NFC (#162411)
2025-10-07 22:24:52 -07:00
RISCVInstrInfoZalasr.td
[RISCV][GISel] Add manual isel for s8/s16/s32 load/store for the GPR bank. (#161995)
2025-10-07 21:30:09 -07:00
RISCVInstrInfoZb.td
[RISCV] Enable PACK isel patterns for P extension. (#173064)
2025-12-21 23:40:30 -08:00
RISCVInstrInfoZc.td
[RISCV] Remove extra operands from Zcb compression patterns. NFC (#150541)
2025-07-24 18:03:30 -07:00
RISCVInstrInfoZclsd.td
…
RISCVInstrInfoZcmop.td
[RISCV] Add underscores to instructions names for Zimop/Zcmop. (#155289)
2025-08-25 14:06:28 -07:00
RISCVInstrInfoZfa.td
…
RISCVInstrInfoZfbfmin.td
[RISCV][NFC] Push riscv_selectcc PatFrag Inwards (#175902)
2026-01-14 10:22:47 -08:00
RISCVInstrInfoZfh.td
[RISCV] Enable rematerialization for scalar loads (#166774)
2025-11-24 18:14:19 +08:00
RISCVInstrInfoZibi.td
[RISCV][NFC] Push riscv_selectcc PatFrag Inwards (#175902)
2026-01-14 10:22:47 -08:00
RISCVInstrInfoZicbo.td
[RISCV][NFC] Cleanup Negative Predicate Names (#155017)
2025-08-22 14:46:41 -07:00
RISCVInstrInfoZicfiss.td
[RISCV] Remove a couple of custom instruction decoders (NFC) (#158483)
2025-09-15 00:57:31 +03:00
RISCVInstrInfoZicond.td
…
RISCVInstrInfoZilsd.td
[llvm][RISCV] Implement Zilsd load/store pair optimization (#158640)
2025-11-21 05:04:05 +00:00
RISCVInstrInfoZimop.td
[RISCV] Add underscores to instructions names for Zimop/Zcmop. (#155289)
2025-08-25 14:06:28 -07:00
RISCVInstrInfoZk.td
…
RISCVInstrInfoZvfbf.td
[NFC][RISCV] Unify all zvfbfa vl patterns and sd node patterns (#171072)
2025-12-11 15:58:06 +08:00
RISCVInstrInfoZvfofp8min.td
[llvm][RISCV] Support Zvfofp8min llvm intrinsics and codegen (#172585)
2025-12-24 02:59:25 +00:00
RISCVInstrInfoZvk.td
[RISCV] Remove duplicate vsha2ch/vsha2cl/vsha2ms i32 patterns. NFC (#151835)
2025-08-02 21:53:58 -07:00
RISCVInstrInfoZvqdotq.td
[RISCV] Remove outdated comment in RISCVInstrInfoZvqdotq.td.
2025-12-17 09:26:06 +08:00
RISCVInstrPredicates.td
[RISCV] Guard zero-stride load SchedPredicate with subtarget feature as well (#172111)
2025-12-16 22:32:20 +00:00
RISCVInterleavedAccess.cpp
[IR] Replace alignment argument with attribute on masked intrinsics (#163802)
2025-10-20 08:50:09 +00:00
RISCVISelDAGToDAG.cpp
[RISCV] Add SimplifyDemandedBits and hasAllNBitUsers support for CLSW. (#174542)
2026-01-06 17:03:23 -08:00
RISCVISelDAGToDAG.h
[RISCV] Support XSfmm LLVM IR and CodeGen (#143069)
2025-10-14 02:01:57 +00:00
RISCVISelLowering.cpp
[RISCV][llvm] Support select codegen for P extension (#175741)
2026-01-14 14:05:45 +08:00
RISCVISelLowering.h
[TargetLowering] Change the softPromoteHalfType default to true (#175149)
2026-01-11 12:48:26 +01:00
RISCVLandingPadSetup.cpp
…
RISCVLateBranchOpt.cpp
…
RISCVLoadStoreOptimizer.cpp
[RISCV] Generate Xqcilsm multi-word load/store instructions for three or more words (#174789)
2026-01-08 12:53:33 +05:30
RISCVMachineFunctionInfo.cpp
…
RISCVMachineFunctionInfo.h
[Target] Add "override" where appropriate (NFC) (#165083)
2025-10-25 06:23:43 -07:00
RISCVMachineScheduler.cpp
[RISCV] Schedule RVV instructions with compatible vtype/vl first
2026-01-12 12:02:39 +08:00
RISCVMachineScheduler.h
[RISCV] Schedule RVV instructions with compatible vtype/vl first
2026-01-12 12:02:39 +08:00
RISCVMacroFusion.td
[RISCV] add more generic macrofusions (#151140)
2025-08-06 14:46:34 -04:00
RISCVMakeCompressible.cpp
[RISCV] Adjust base cost for Xqcilo loads/stores in RISCVMakeCompressible (#175572)
2026-01-13 06:34:18 +05:30
RISCVMergeBaseOffset.cpp
[RISCV] Detect QC_E_ADDAI and fold in RISCVMergeBaseOffset (#175496)
2026-01-12 22:43:38 +05:30
RISCVMoveMerger.cpp
[RISCV] Minor refactor of RISCVMoveMerge::mergePairedInsns. (#154467)
2025-08-20 09:07:58 -07:00
RISCVOptWInstrs.cpp
[RISCV] Add SimplifyDemandedBits and hasAllNBitUsers support for CLSW. (#174542)
2026-01-06 17:03:23 -08:00
RISCVPassRegistry.def
[RISCV][NewPM] Port RISCVCodeGenPrepare to the new pass manager (#168381)
2025-11-19 06:51:18 +00:00
RISCVPfmCounters.td
…
RISCVPostRAExpandPseudoInsts.cpp
…
RISCVProcessors.td
[RISCV] Add missing arch features of tt-ascalon-d8 (#176071)
2026-01-15 10:05:42 +00:00
RISCVProfiles.td
…
RISCVPromoteConstant.cpp
[RISCV] Introduce pass to promote double constants to a global array (#160536)
2025-11-05 14:31:17 +00:00
RISCVPushPopOptimizer.cpp
…
RISCVRedundantCopyElimination.cpp
[RISCV] Add support for Zibi experimental extension in RISCVRedundantCopyElimination (#174920)
2026-01-09 14:00:53 +08:00
RISCVRegisterInfo.cpp
[RISCV][llvm] Support frame index in zilsd optimizer (#174073)
2026-01-10 00:27:48 +08:00
RISCVRegisterInfo.h
[llvm][RISCV] Implement Zilsd load/store pair optimization (#158640)
2025-11-21 05:04:05 +00:00
RISCVRegisterInfo.td
[RISCV] Change FPR256 to use the same allocation order as FPR16/32/64/128. (#176097)
2026-01-15 07:35:12 -08:00
RISCVSchedAndes45.td
[RISCV] Update Andes45 vector load/stores scheduling info (#173806)
2026-01-05 09:20:44 +08:00
RISCVSchedGenericOOO.td
…
RISCVSchedMIPSP8700.td
…
RISCVSchedRocket.td
…
RISCVSchedSiFive7.td
[RISCV] LMUL lists for indexed and strided loads (#169756)
2025-12-05 13:10:22 -08:00
RISCVSchedSiFiveP400.td
…
RISCVSchedSiFiveP500.td
…
RISCVSchedSiFiveP600.td
[RISCV] Fix wrong use of SiFiveP400GetVLMAX in RISCVSchedSiFiveP600 (#171562)
2025-12-10 13:59:13 +08:00
RISCVSchedSiFiveP800.td
…
RISCVSchedSpacemitX60.td
[RISCV] Assign separate latencies for vector COPYs in SpacemitX60 scheduling model (#172556)
2025-12-18 07:04:42 -08:00
RISCVSchedSyntacoreSCR1.td
…
RISCVSchedSyntacoreSCR7.td
…
RISCVSchedSyntacoreSCR345.td
…
RISCVSchedTTAscalonD8.td
[RISCV] LMUL lists for indexed and strided loads (#169756)
2025-12-05 13:10:22 -08:00
RISCVSchedule.td
[RISCV] Assign separate latencies for vector COPYs in SpacemitX60 scheduling model (#172556)
2025-12-18 07:04:42 -08:00
RISCVScheduleV.td
[RISCV] LMUL lists for indexed and strided loads (#169756)
2025-12-05 13:10:22 -08:00
RISCVScheduleXSf.td
[RISCV] Add LLVM IR intrinsics and codegen for XSfvfexp* and XSfvfexpa* (#164499)
2025-10-24 18:09:03 +00:00
RISCVScheduleZb.td
…
RISCVScheduleZvk.td
…
RISCVSchedXiangShanNanHu.td
…
RISCVSelectionDAGInfo.cpp
[SelectionDAG] Verify SDTCisVT and SDTCVecEltisVT constraints (#150125)
2025-11-16 18:26:03 +03:00
RISCVSelectionDAGInfo.h
[RISCV] Implement EmitTargetCodeForMemset for Xqcilsm (#151555)
2025-08-04 12:51:14 +05:30
RISCVSubtarget.cpp
[RISCV] Handle codegen for Big Endian (#172668)
2025-12-19 19:35:01 +01:00
RISCVSubtarget.h
[RISCV] Handle codegen for Big Endian (#172668)
2025-12-19 19:35:01 +01:00
RISCVSystemOperands.td
[RISCV] AI Foundry ET extensions for RISC-V (#174571)
2026-01-13 12:54:11 -08:00
RISCVTargetMachine.cpp
[RISCV] Add a custom pre-ra scheduler
2026-01-12 12:00:22 +08:00
RISCVTargetMachine.h
…
RISCVTargetObjectFile.cpp
…
RISCVTargetObjectFile.h
[RISC-V][Mach-O] Implement and select the RISCVMachOTargetObjectFile. (#174677)
2026-01-06 22:02:55 -08:00
RISCVTargetTransformInfo.cpp
[RISCV] Improve cost modeling of RISCVTTIImpl::getConstantPoolLoadCost() (#174438)
2026-01-07 16:50:47 -08:00
RISCVTargetTransformInfo.h
[RISCV] Improve cost modeling of RISCVTTIImpl::getConstantPoolLoadCost() (#174438)
2026-01-07 16:50:47 -08:00
RISCVVectorMaskDAGMutation.cpp
…
RISCVVectorPeephole.cpp
[RISCV] Commute Src in foldVMV_V_V (#170536)
2025-12-04 14:39:23 +08:00
RISCVVLOptimizer.cpp
[RISCV] Only reduce VLs of instructions with demanded VLs (#168693)
2025-11-20 03:49:59 +00:00
RISCVVMV0Elimination.cpp
…
RISCVVSETVLIInfoAnalysis.cpp
[RISCV][NFC] Add RISCVVSETVLIInfoAnalysis
2026-01-12 12:00:55 +08:00
RISCVVSETVLIInfoAnalysis.h
[RISCV][NFC] Add RISCVVSETVLIInfoAnalysis
2026-01-12 12:00:55 +08:00
RISCVZacasABIFix.cpp
…
RISCVZilsdOptimizer.cpp
[RISCV][llvm] Support frame index in zilsd optimizer (#174073)
2026-01-10 00:27:48 +08:00