d748c81218
The 16-bit immediate operand of s_waitcnt_depctr / s_wait_alu has some unused bits. Previously codegen would set these bits to 1, but setting them to 0 matches the SP3 assembler behaviour better, which in turn means that we can print them using the human readable SP3 syntax: s_wait_alu 0xfffd ; unused bits set to 1 s_wait_alu 0xff9d ; unused bits set to 0 s_wait_alu depctr_va_vcc(0) ; unused bits set to 0, human readable Note that the set of unused bits changed between GFX10.1 and GFX10.3.
93 lines
4.1 KiB
LLVM
93 lines
4.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
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; RUN: not --crash llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -global-isel=0 < %s 2>&1 | FileCheck -check-prefix=GFX9-SDAG-ERR %s
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; RUN: not llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -global-isel=1 -new-reg-bank-select < %s 2>&1 | FileCheck -check-prefix=GFX9-GISEL-ERR %s
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; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -mattr=+architected-sgprs -global-isel=0 < %s | FileCheck -check-prefix=GFX9 %s
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; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -mattr=+architected-sgprs -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefix=GFX9 %s
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; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 -global-isel=0 < %s | FileCheck -check-prefix=GFX1200 %s
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; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefix=GFX1200 %s
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; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1250 -global-isel=0 < %s | FileCheck -check-prefix=GFX1250 %s
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; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1250 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefix=GFX1250 %s
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; GFX9-SDAG-ERR: LLVM ERROR: Cannot select: intrinsic %llvm.amdgcn.wave.id
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; GFX9-GISEL-ERR: LLVM ERROR: unable to legalize instruction: {{.*}} = G_INTRINSIC intrinsic(@llvm.amdgcn.wave.id)
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define amdgpu_cs void @test_wave_id(ptr addrspace(1) %out) {
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; GFX9-LABEL: test_wave_id:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_bfe_u32 s0, ttmp8, 0x50019
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; GFX9-NEXT: v_mov_b32_e32 v2, s0
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; GFX9-NEXT: global_store_dword v[0:1], v2, off
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; GFX9-NEXT: s_endpgm
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;
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; GFX1200-LABEL: test_wave_id:
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; GFX1200: ; %bb.0:
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; GFX1200-NEXT: s_bfe_u32 s0, ttmp8, 0x50019
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; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; GFX1200-NEXT: v_mov_b32_e32 v2, s0
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; GFX1200-NEXT: global_store_b32 v[0:1], v2, off
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; GFX1200-NEXT: s_endpgm
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;
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; GFX1250-LABEL: test_wave_id:
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; GFX1250: ; %bb.0:
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; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
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; GFX1250-NEXT: s_bfe_u32 s0, ttmp8, 0x50019
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; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; GFX1250-NEXT: v_mov_b32_e32 v2, s0
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; GFX1250-NEXT: global_store_b32 v[0:1], v2, off
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; GFX1250-NEXT: s_endpgm
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%waveid = call i32 @llvm.amdgcn.wave.id()
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store i32 %waveid, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_gfx void @test_wave_id_callable(ptr addrspace(1) %out) {
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; GFX9-LABEL: test_wave_id_callable:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-NEXT: s_bfe_u32 s34, ttmp8, 0x50019
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; GFX9-NEXT: v_mov_b32_e32 v2, s34
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; GFX9-NEXT: global_store_dword v[0:1], v2, off
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; GFX9-NEXT: s_waitcnt vmcnt(0)
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; GFX9-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX1200-LABEL: test_wave_id_callable:
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; GFX1200: ; %bb.0:
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; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX1200-NEXT: s_wait_expcnt 0x0
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; GFX1200-NEXT: s_wait_samplecnt 0x0
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; GFX1200-NEXT: s_wait_bvhcnt 0x0
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; GFX1200-NEXT: s_wait_kmcnt 0x0
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; GFX1200-NEXT: s_bfe_u32 s0, ttmp8, 0x50019
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; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
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; GFX1200-NEXT: v_mov_b32_e32 v2, s0
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; GFX1200-NEXT: global_store_b32 v[0:1], v2, off
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; GFX1200-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX1250-LABEL: test_wave_id_callable:
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; GFX1250: ; %bb.0:
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; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX1250-NEXT: s_wait_kmcnt 0x0
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; GFX1250-NEXT: s_bfe_u32 s0, ttmp8, 0x50019
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; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; GFX1250-NEXT: v_mov_b32_e32 v2, s0
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; GFX1250-NEXT: global_store_b32 v[0:1], v2, off
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; GFX1250-NEXT: s_set_pc_i64 s[30:31]
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; GFX12-LABEL: test_wave_id_callable:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX12-NEXT: s_wait_expcnt 0x0
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; GFX12-NEXT: s_wait_samplecnt 0x0
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; GFX12-NEXT: s_wait_bvhcnt 0x0
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; GFX12-NEXT: s_wait_kmcnt 0x0
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; GFX12-NEXT: s_bfe_u32 s0, ttmp8, 0x50019
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; GFX12-NEXT: s_wait_alu 0xfffe
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; GFX12-NEXT: v_mov_b32_e32 v2, s0
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; GFX12-NEXT: global_store_b32 v[0:1], v2, off
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; GFX12-NEXT: s_setpc_b64 s[30:31]
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%waveid = call i32 @llvm.amdgcn.wave.id()
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store i32 %waveid, ptr addrspace(1) %out
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ret void
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}
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declare i32 @llvm.amdgcn.wave.id()
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