e4a4bb0f6d
This patch optimizes vector addition operations involving **`all-ones`**
vectors by leveraging the generation of vectors of -1s(using `xxleqv`,
which is cheaper than generating vectors of 1s(`vspltisw`). These are
the respective vector types.
`v2i64`: **`A + vector {1, 1}`**
`v4i32`: **`A + vector {1, 1, 1, 1}`**
`v8i16`: **`A + vector {1, 1, 1, 1, 1, 1, 1, 1}`**
`v16i8`: **`A + vector {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1}`**
The optimized version replaces `vspltisw (4 cycles)` with `xxleqv (2
cycles)` using the following identity:
`A - (-1) = A + 1`.
---------
Co-authored-by: himadhith <himadhith.v@ibm.com>
Co-authored-by: Tony Varghese <tonypalampalliyil@gmail.com>
117 lines
3.5 KiB
LLVM
117 lines
3.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s --check-prefixes=ALL,VSX
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s --check-prefixes=ALL,NOVSX
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; Check VMX 64-bit integer operations
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define <2 x i64> @test_add(<2 x i64> %x, <2 x i64> %y) nounwind {
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; ALL-LABEL: test_add:
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; ALL: # %bb.0:
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; ALL-NEXT: vaddudm 2, 2, 3
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; ALL-NEXT: blr
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%result = add <2 x i64> %x, %y
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ret <2 x i64> %result
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}
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define <2 x i64> @increment_by_one(<2 x i64> %x) nounwind {
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; VSX-LABEL: increment_by_one:
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; VSX: # %bb.0:
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; VSX-NEXT: xxleqv 35, 35, 35
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; VSX-NEXT: vsubudm 2, 2, 3
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; VSX-NEXT: blr
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;
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; NOVSX-LABEL: increment_by_one:
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; NOVSX: # %bb.0:
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; NOVSX-NEXT: addis 3, 2, .LCPI1_0@toc@ha
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; NOVSX-NEXT: addi 3, 3, .LCPI1_0@toc@l
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; NOVSX-NEXT: lvx 3, 0, 3
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; NOVSX-NEXT: vaddudm 2, 2, 3
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; NOVSX-NEXT: blr
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%result = add <2 x i64> %x, <i64 1, i64 1>
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ret <2 x i64> %result
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}
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define <2 x i64> @increment_by_val(<2 x i64> %x, i64 %val) nounwind {
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; VSX-LABEL: increment_by_val:
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; VSX: # %bb.0:
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; VSX-NEXT: mtfprd 0, 5
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; VSX-NEXT: xxspltd 35, 0, 0
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; VSX-NEXT: vaddudm 2, 2, 3
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; VSX-NEXT: blr
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;
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; NOVSX-LABEL: increment_by_val:
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; NOVSX: # %bb.0:
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; NOVSX-NEXT: addi 3, 1, -16
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; NOVSX-NEXT: std 5, -8(1)
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; NOVSX-NEXT: std 5, -16(1)
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; NOVSX-NEXT: lvx 3, 0, 3
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; NOVSX-NEXT: vaddudm 2, 2, 3
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; NOVSX-NEXT: blr
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%tmpvec = insertelement <2 x i64> <i64 0, i64 0>, i64 %val, i32 0
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%tmpvec2 = insertelement <2 x i64> %tmpvec, i64 %val, i32 1
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%result = add <2 x i64> %x, %tmpvec2
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ret <2 x i64> %result
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; FIXME: This is currently generating the following instruction sequence
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; std 5, -8(1)
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; std 5, -16(1)
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; addi 3, 1, -16
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; ori 2, 2, 0
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; lxvd2x 35, 0, 3
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; vaddudm 2, 2, 3
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; blr
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; This will almost certainly cause a load-hit-store hazard.
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; Since val is a value parameter, it should not need to be
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; saved onto the stack at all (unless we're using this to set
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; up the vector register). Instead, it would be better to splat
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; the value into a vector register.
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}
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define <2 x i64> @test_sub(<2 x i64> %x, <2 x i64> %y) nounwind {
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; ALL-LABEL: test_sub:
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; ALL: # %bb.0:
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; ALL-NEXT: vsubudm 2, 2, 3
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; ALL-NEXT: blr
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%result = sub <2 x i64> %x, %y
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ret <2 x i64> %result
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}
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define <2 x i64> @decrement_by_one(<2 x i64> %x) nounwind {
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; VSX-LABEL: decrement_by_one:
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; VSX: # %bb.0:
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; VSX-NEXT: xxleqv 35, 35, 35
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; VSX-NEXT: vsubudm 2, 2, 3
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; VSX-NEXT: blr
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;
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; NOVSX-LABEL: decrement_by_one:
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; NOVSX: # %bb.0:
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; NOVSX-NEXT: addis 3, 2, .LCPI4_0@toc@ha
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; NOVSX-NEXT: addi 3, 3, .LCPI4_0@toc@l
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; NOVSX-NEXT: lvx 3, 0, 3
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; NOVSX-NEXT: vsubudm 2, 2, 3
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; NOVSX-NEXT: blr
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%result = sub <2 x i64> %x, <i64 -1, i64 -1>
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ret <2 x i64> %result
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}
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define <2 x i64> @decrement_by_val(<2 x i64> %x, i64 %val) nounwind {
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; VSX-LABEL: decrement_by_val:
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; VSX: # %bb.0:
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; VSX-NEXT: mtfprd 0, 5
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; VSX-NEXT: xxspltd 35, 0, 0
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; VSX-NEXT: vsubudm 2, 2, 3
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; VSX-NEXT: blr
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;
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; NOVSX-LABEL: decrement_by_val:
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; NOVSX: # %bb.0:
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; NOVSX-NEXT: addi 3, 1, -16
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; NOVSX-NEXT: std 5, -8(1)
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; NOVSX-NEXT: std 5, -16(1)
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; NOVSX-NEXT: lvx 3, 0, 3
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; NOVSX-NEXT: vsubudm 2, 2, 3
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; NOVSX-NEXT: blr
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%tmpvec = insertelement <2 x i64> <i64 0, i64 0>, i64 %val, i32 0
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%tmpvec2 = insertelement <2 x i64> %tmpvec, i64 %val, i32 1
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%result = sub <2 x i64> %x, %tmpvec2
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ret <2 x i64> %result
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}
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