c2e84072bd
`-riscv-fp-imm-cost` controls the threshold at which the constant pool is used for float constants rather than generating directly (typically into a GPR followed by an `fmv`). The value used for this knob indicates the number of instructions that can be used to produce the value (otherwise we fall back to the constant pool). Upping to to 3 covers a huge number of additional constants (see <https://github.com/llvm/llvm-project/issues/153402>), e.g. most whole numbers which can be generated through lui+shift+fmv. As in general we struggle with efficient code generation for constant pool accesses, reducing the number of constant pool accesses is beneficial. We are typically replacing a two-instruction sequence (which includes a load) with a three instruction sequence (two simple arithmetic operations plus a fmv), which. The CHECK prefixes for various tests had to be updated to avoid conflicts leading to check lines being dropped altogether (see <https://github.com/llvm/llvm-project/pull/159321> for a change to update_llc_test_checks to aid diagnosing this).
174 lines
5.7 KiB
LLVM
174 lines
5.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
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; RUN: -target-abi=ilp32d | FileCheck %s --check-prefix=CHECK32D
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; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
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; RUN: -target-abi=lp64d | FileCheck %s --check-prefix=CHECK64D
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; RUN: llc -mtriple=riscv32 -mattr=+zdinx -verify-machineinstrs < %s \
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; RUN: -target-abi=ilp32 | FileCheck --check-prefix=CHECKRV32ZDINX %s
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; RUN: llc -mtriple=riscv64 -mattr=+zdinx -verify-machineinstrs < %s \
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; RUN: -target-abi=lp64 | FileCheck --check-prefix=CHECKRV64ZDINX %s
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define double @double_imm() nounwind {
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; CHECK32D-LABEL: double_imm:
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; CHECK32D: # %bb.0:
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; CHECK32D-NEXT: lui a0, %hi(.LCPI0_0)
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; CHECK32D-NEXT: fld fa0, %lo(.LCPI0_0)(a0)
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; CHECK32D-NEXT: ret
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;
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; CHECK64D-LABEL: double_imm:
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; CHECK64D: # %bb.0:
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; CHECK64D-NEXT: lui a0, %hi(.LCPI0_0)
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; CHECK64D-NEXT: fld fa0, %lo(.LCPI0_0)(a0)
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; CHECK64D-NEXT: ret
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;
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; CHECKRV32ZDINX-LABEL: double_imm:
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; CHECKRV32ZDINX: # %bb.0:
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; CHECKRV32ZDINX-NEXT: lui a0, 345155
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; CHECKRV32ZDINX-NEXT: lui a1, 262290
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; CHECKRV32ZDINX-NEXT: addi a0, a0, -744
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; CHECKRV32ZDINX-NEXT: addi a1, a1, 507
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; CHECKRV32ZDINX-NEXT: ret
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;
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; CHECKRV64ZDINX-LABEL: double_imm:
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; CHECKRV64ZDINX: # %bb.0:
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; CHECKRV64ZDINX-NEXT: lui a0, %hi(.LCPI0_0)
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; CHECKRV64ZDINX-NEXT: ld a0, %lo(.LCPI0_0)(a0)
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; CHECKRV64ZDINX-NEXT: ret
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ret double 3.1415926535897931159979634685441851615905761718750
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}
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define double @double_imm_op(double %a) nounwind {
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; CHECK32D-LABEL: double_imm_op:
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; CHECK32D: # %bb.0:
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; CHECK32D-NEXT: lui a0, %hi(.LCPI1_0)
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; CHECK32D-NEXT: fld fa5, %lo(.LCPI1_0)(a0)
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; CHECK32D-NEXT: fadd.d fa0, fa0, fa5
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; CHECK32D-NEXT: ret
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;
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; CHECK64D-LABEL: double_imm_op:
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; CHECK64D: # %bb.0:
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; CHECK64D-NEXT: li a0, 1023
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; CHECK64D-NEXT: slli a0, a0, 52
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; CHECK64D-NEXT: fmv.d.x fa5, a0
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; CHECK64D-NEXT: fadd.d fa0, fa0, fa5
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; CHECK64D-NEXT: ret
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;
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; CHECKRV32ZDINX-LABEL: double_imm_op:
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; CHECKRV32ZDINX: # %bb.0:
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; CHECKRV32ZDINX-NEXT: lui a2, %hi(.LCPI1_0)
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; CHECKRV32ZDINX-NEXT: lw a4, %lo(.LCPI1_0)(a2)
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; CHECKRV32ZDINX-NEXT: addi a2, a2, %lo(.LCPI1_0)
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; CHECKRV32ZDINX-NEXT: lw a5, 4(a2)
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; CHECKRV32ZDINX-NEXT: fadd.d a0, a0, a4
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; CHECKRV32ZDINX-NEXT: ret
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;
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; CHECKRV64ZDINX-LABEL: double_imm_op:
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; CHECKRV64ZDINX: # %bb.0:
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; CHECKRV64ZDINX-NEXT: li a1, 1023
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; CHECKRV64ZDINX-NEXT: slli a1, a1, 52
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; CHECKRV64ZDINX-NEXT: fadd.d a0, a0, a1
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; CHECKRV64ZDINX-NEXT: ret
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%1 = fadd double %a, 1.0
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ret double %1
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}
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define double @double_positive_zero(ptr %pd) nounwind {
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; CHECK32D-LABEL: double_positive_zero:
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; CHECK32D: # %bb.0:
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; CHECK32D-NEXT: fcvt.d.w fa0, zero
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; CHECK32D-NEXT: ret
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;
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; CHECK64D-LABEL: double_positive_zero:
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; CHECK64D: # %bb.0:
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; CHECK64D-NEXT: fmv.d.x fa0, zero
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; CHECK64D-NEXT: ret
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;
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; CHECKRV32ZDINX-LABEL: double_positive_zero:
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; CHECKRV32ZDINX: # %bb.0:
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; CHECKRV32ZDINX-NEXT: li a0, 0
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; CHECKRV32ZDINX-NEXT: li a1, 0
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; CHECKRV32ZDINX-NEXT: ret
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;
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; CHECKRV64ZDINX-LABEL: double_positive_zero:
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; CHECKRV64ZDINX: # %bb.0:
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; CHECKRV64ZDINX-NEXT: li a0, 0
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; CHECKRV64ZDINX-NEXT: ret
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ret double 0.0
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}
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define double @double_negative_zero(ptr %pd) nounwind {
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; CHECK32D-LABEL: double_negative_zero:
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; CHECK32D: # %bb.0:
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; CHECK32D-NEXT: fcvt.d.w fa5, zero
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; CHECK32D-NEXT: fneg.d fa0, fa5
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; CHECK32D-NEXT: ret
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;
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; CHECK64D-LABEL: double_negative_zero:
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; CHECK64D: # %bb.0:
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; CHECK64D-NEXT: fmv.d.x fa5, zero
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; CHECK64D-NEXT: fneg.d fa0, fa5
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; CHECK64D-NEXT: ret
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;
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; CHECKRV32ZDINX-LABEL: double_negative_zero:
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; CHECKRV32ZDINX: # %bb.0:
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; CHECKRV32ZDINX-NEXT: lui a1, 524288
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; CHECKRV32ZDINX-NEXT: li a0, 0
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; CHECKRV32ZDINX-NEXT: ret
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;
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; CHECKRV64ZDINX-LABEL: double_negative_zero:
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; CHECKRV64ZDINX: # %bb.0:
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; CHECKRV64ZDINX-NEXT: fneg.d a0, zero
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; CHECKRV64ZDINX-NEXT: ret
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ret double -0.0
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}
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define dso_local double @negzero_sel(i16 noundef %a, double noundef %d) nounwind {
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; CHECK32D-LABEL: negzero_sel:
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; CHECK32D: # %bb.0: # %entry
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; CHECK32D-NEXT: slli a0, a0, 16
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; CHECK32D-NEXT: beqz a0, .LBB4_2
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; CHECK32D-NEXT: # %bb.1: # %entry
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; CHECK32D-NEXT: fcvt.d.w fa5, zero
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; CHECK32D-NEXT: fneg.d fa0, fa5
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; CHECK32D-NEXT: .LBB4_2: # %entry
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; CHECK32D-NEXT: ret
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;
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; CHECK64D-LABEL: negzero_sel:
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; CHECK64D: # %bb.0: # %entry
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; CHECK64D-NEXT: slli a0, a0, 48
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; CHECK64D-NEXT: beqz a0, .LBB4_2
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; CHECK64D-NEXT: # %bb.1: # %entry
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; CHECK64D-NEXT: fmv.d.x fa5, zero
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; CHECK64D-NEXT: fneg.d fa0, fa5
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; CHECK64D-NEXT: .LBB4_2: # %entry
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; CHECK64D-NEXT: ret
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;
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; CHECKRV32ZDINX-LABEL: negzero_sel:
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; CHECKRV32ZDINX: # %bb.0: # %entry
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; CHECKRV32ZDINX-NEXT: slli a0, a0, 16
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; CHECKRV32ZDINX-NEXT: beqz a0, .LBB4_2
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; CHECKRV32ZDINX-NEXT: # %bb.1: # %entry
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; CHECKRV32ZDINX-NEXT: fneg.d a2, zero
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; CHECKRV32ZDINX-NEXT: j .LBB4_3
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; CHECKRV32ZDINX-NEXT: .LBB4_2:
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; CHECKRV32ZDINX-NEXT: mv a3, a2
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; CHECKRV32ZDINX-NEXT: mv a2, a1
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; CHECKRV32ZDINX-NEXT: .LBB4_3: # %entry
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; CHECKRV32ZDINX-NEXT: mv a0, a2
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; CHECKRV32ZDINX-NEXT: mv a1, a3
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; CHECKRV32ZDINX-NEXT: ret
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;
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; CHECKRV64ZDINX-LABEL: negzero_sel:
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; CHECKRV64ZDINX: # %bb.0: # %entry
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; CHECKRV64ZDINX-NEXT: slli a2, a0, 48
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; CHECKRV64ZDINX-NEXT: mv a0, a1
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; CHECKRV64ZDINX-NEXT: beqz a2, .LBB4_2
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; CHECKRV64ZDINX-NEXT: # %bb.1: # %entry
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; CHECKRV64ZDINX-NEXT: fneg.d a0, zero
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; CHECKRV64ZDINX-NEXT: .LBB4_2: # %entry
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; CHECKRV64ZDINX-NEXT: ret
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entry:
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%tobool.not = icmp eq i16 %a, 0
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%d. = select i1 %tobool.not, double %d, double -0.000000e+00
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ret double %d.
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}
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