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llvm-project/llvm/test/Transforms/StraightLineStrengthReduce/slsr-add.ll
Fei Peng f803e463f9
Reland "Redesign Straight-Line Strength Reduction (SLSR) (#162930)" (#169614) 
This PR implements parts of
https://github.com/llvm/llvm-project/issues/162376

- **Broader equivalence than constant index deltas**:
- Add Base-delta and Stride-delta matching for Add and GEP forms using
ScalarEvolution deltas.
- Reuse enabled for both constant and variable deltas when an available
IR value dominates the user.
- **Dominance-aware dictionary instead of linear scans**:
  - Tuple-keyed candidate dictionary grouped by basic block.
- Walk the immediate-dominator chain to find the nearest dominating
basis quickly and deterministically.
- **Simple cost model and best-rewrite selection**:
- Score candidate expressions and rewrites; select the highest-profit
rewrite per instruction.
- Skip rewriting when expressions are already foldable or
high-efficiency.
- **Path compression for better ILP**:
- Compress chains of rewrites to a deeper dominating basis when a
constant delta exists along the path, reducing dependent bumps on
critical paths.
- **Dependency-aware rewrite ordering**:
- Build a dependency graph (basis, stride, variable delta producers) and
rewrite in topological order.
- This dependency graph will be needed by the next PR that adds partial
strength reduction.
- **Correctness enhencment**
- Fix a correctness issue that reusing instructions with the same SCEV
may introduce poison.

---------

Co-authored-by: Kazu Hirata <kazu@google.com>
2025-12-08 16:07:27 -06:00

294 lines
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -passes=slsr,gvn -S | FileCheck %s
; RUN: opt < %s -passes='slsr,gvn' -S | FileCheck %s
target datalayout = "e-i64:64-v16:16-v32:32-n16:32:64"
; Index Delta
define void @shl(i32 %b, i32 %s) {
; CHECK-LABEL: @shl(
; CHECK-NEXT: [[T1:%.*]] = add i32 [[B:%.*]], [[S:%.*]]
; CHECK-NEXT: call void @foo(i32 [[T1]])
; CHECK-NEXT: [[T2:%.*]] = add i32 [[T1]], [[S]]
; CHECK-NEXT: call void @foo(i32 [[T2]])
; CHECK-NEXT: ret void
;
%t1 = add i32 %b, %s
call void @foo(i32 %t1)
%s2 = shl i32 %s, 1
%t2 = add i32 %b, %s2
call void @foo(i32 %t2)
ret void
}
define void @stride_is_2s(i32 %b, i32 %s) {
; CHECK-LABEL: @stride_is_2s(
; CHECK-NEXT: [[S2:%.*]] = shl i32 [[S:%.*]], 1
; CHECK-NEXT: [[T1:%.*]] = add i32 [[B:%.*]], [[S2]]
; CHECK-NEXT: call void @foo(i32 [[T1]])
; CHECK-NEXT: [[T2:%.*]] = add i32 [[T1]], [[S2]]
; CHECK-NEXT: call void @foo(i32 [[T2]])
; CHECK-NEXT: [[T3:%.*]] = add i32 [[T2]], [[S2]]
; CHECK-NEXT: call void @foo(i32 [[T3]])
; CHECK-NEXT: ret void
;
%s2 = shl i32 %s, 1
%t1 = add i32 %b, %s2
call void @foo(i32 %t1)
%s4 = shl i32 %s, 2
%t2 = add i32 %b, %s4
call void @foo(i32 %t2)
%s6 = mul i32 %s, 6
%t3 = add i32 %b, %s6
call void @foo(i32 %t3)
ret void
}
define void @stride_is_3s(i32 %b, i32 %s) {
; CHECK-LABEL: @stride_is_3s(
; CHECK-NEXT: [[T1:%.*]] = add i32 [[S:%.*]], [[B:%.*]]
; CHECK-NEXT: call void @foo(i32 [[T1]])
; CHECK-NEXT: [[TMP1:%.*]] = mul i32 [[S]], 3
; CHECK-NEXT: [[T2:%.*]] = add i32 [[T1]], [[TMP1]]
; CHECK-NEXT: call void @foo(i32 [[T2]])
; CHECK-NEXT: [[T3:%.*]] = add i32 [[T2]], [[TMP1]]
; CHECK-NEXT: call void @foo(i32 [[T3]])
; CHECK-NEXT: ret void
;
%t1 = add i32 %s, %b
call void @foo(i32 %t1)
%s4 = shl i32 %s, 2
%t2 = add i32 %s4, %b
call void @foo(i32 %t2)
%s7 = mul i32 %s, 7
%t3 = add i32 %s7, %b
call void @foo(i32 %t3)
ret void
}
; foo(b + 6 * s);
; foo(b + 4 * s);
; foo(b + 2 * s);
; =>
; t1 = b + 6 * s;
; foo(t1);
; s2 = 2 * s;
; t2 = t1 - s2;
; foo(t2);
; t3 = t2 - s2;
; foo(t3);
define void @stride_is_minus_2s(i32 %b, i32 %s) {
; CHECK-LABEL: @stride_is_minus_2s(
; CHECK-NEXT: [[S6:%.*]] = mul i32 [[S:%.*]], 6
; CHECK-NEXT: [[T1:%.*]] = add i32 [[B:%.*]], [[S6]]
; CHECK-NEXT: call void @foo(i32 [[T1]])
; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[S]], 1
; CHECK-NEXT: [[T2:%.*]] = sub i32 [[T1]], [[TMP1]]
; CHECK-NEXT: call void @foo(i32 [[T2]])
; CHECK-NEXT: [[T3:%.*]] = sub i32 [[T2]], [[TMP1]]
; CHECK-NEXT: call void @foo(i32 [[T3]])
; CHECK-NEXT: ret void
;
%s6 = mul i32 %s, 6
%t1 = add i32 %b, %s6
call void @foo(i32 %t1)
%s4 = shl i32 %s, 2
%t2 = add i32 %b, %s4
call void @foo(i32 %t2)
%s2 = shl i32 %s, 1
%t3 = add i32 %b, %s2
call void @foo(i32 %t3)
ret void
}
; TODO: This pass is targeted at simple address-calcs, so it is artificially limited to
; match scalar values. The code could be modified to handle vector types too.
define void @stride_is_minus_2s_vec(<2 x i32> %b, <2 x i32> %s) {
; CHECK-LABEL: @stride_is_minus_2s_vec(
; CHECK-NEXT: [[S6:%.*]] = mul <2 x i32> [[S:%.*]], splat (i32 6)
; CHECK-NEXT: [[T1:%.*]] = add <2 x i32> [[B:%.*]], [[S6]]
; CHECK-NEXT: call void @voo(<2 x i32> [[T1]])
; CHECK-NEXT: [[S4:%.*]] = shl <2 x i32> [[S]], splat (i32 2)
; CHECK-NEXT: [[T2:%.*]] = add <2 x i32> [[B]], [[S4]]
; CHECK-NEXT: call void @voo(<2 x i32> [[T2]])
; CHECK-NEXT: [[S2:%.*]] = shl <2 x i32> [[S]], splat (i32 1)
; CHECK-NEXT: [[T3:%.*]] = add <2 x i32> [[B]], [[S2]]
; CHECK-NEXT: call void @voo(<2 x i32> [[T3]])
; CHECK-NEXT: ret void
;
%s6 = mul <2 x i32> %s, <i32 6, i32 6>
%t1 = add <2 x i32> %b, %s6
call void @voo(<2 x i32> %t1)
%s4 = shl <2 x i32> %s, <i32 2, i32 2>
%t2 = add <2 x i32> %b, %s4
call void @voo(<2 x i32> %t2)
%s2 = shl <2 x i32> %s, <i32 1, i32 1>
%t3 = add <2 x i32> %b, %s2
call void @voo(<2 x i32> %t3)
ret void
}
; t = b + (s << 3);
; foo(t);
; foo(b + s);
;
; do not rewrite b + s to t - 7 * s because the latter is more complicated.
define void @simple_enough(i32 %b, i32 %s) {
; CHECK-LABEL: @simple_enough(
; CHECK-NEXT: [[S8:%.*]] = shl i32 [[S:%.*]], 3
; CHECK-NEXT: [[T1:%.*]] = add i32 [[B:%.*]], [[S8]]
; CHECK-NEXT: call void @foo(i32 [[T1]])
; CHECK-NEXT: [[T2:%.*]] = add i32 [[B]], [[S]]
; CHECK-NEXT: call void @foo(i32 [[T2]])
; CHECK-NEXT: ret void
;
%s8 = shl i32 %s, 3
%t1 = add i32 %b, %s8
call void @foo(i32 %t1)
%t2 = add i32 %b, %s
call void @foo(i32 %t2)
ret void
}
define void @slsr_strided_add_128bit(i128 %b, i128 %s) {
; CHECK-LABEL: @slsr_strided_add_128bit(
; CHECK-NEXT: [[S125:%.*]] = shl i128 [[S:%.*]], 125
; CHECK-NEXT: [[T1:%.*]] = add i128 [[B:%.*]], [[S125]]
; CHECK-NEXT: call void @bar(i128 [[T1]])
; CHECK-NEXT: [[T2:%.*]] = add i128 [[T1]], [[S125]]
; CHECK-NEXT: call void @bar(i128 [[T2]])
; CHECK-NEXT: ret void
;
%s125 = shl i128 %s, 125
%s126 = shl i128 %s, 126
%t1 = add i128 %b, %s125
call void @bar(i128 %t1)
%t2 = add i128 %b, %s126
call void @bar(i128 %t2)
ret void
}
declare void @foo(i32)
declare void @voo(<2 x i32>)
declare void @bar(i128)
; Stride Delta
define void @stride_const(i32 %a, ptr %base, i16 %r) {
; Reuse add1 to compute add2
; CHECK-LABEL: @stride_const(
; CHECK-NEXT: [[I1:%.*]] = sext i32 [[A:%.*]] to i64
; CHECK-NEXT: [[I2:%.*]] = mul i64 [[I1]], 2
; CHECK-NEXT: [[BI:%.*]] = ptrtoint ptr [[BASE:%.*]] to i64
; CHECK-NEXT: [[ADD1:%.*]] = add i64 [[BI]], [[I2]]
; CHECK-NEXT: [[ADD2:%.*]] = add i64 [[ADD1]], 8
; CHECK-NEXT: [[ADDR1:%.*]] = inttoptr i64 [[ADD1]] to ptr
; CHECK-NEXT: [[ADDR2:%.*]] = inttoptr i64 [[ADD2]] to ptr
; CHECK-NEXT: store i16 [[R:%.*]], ptr [[ADDR1]], align 2
; CHECK-NEXT: store i16 [[R]], ptr [[ADDR2]], align 2
; CHECK-NEXT: ret void
;
%1 = sext i32 %a to i64
%2 = mul i64 %1, 2
%3 = add i64 %1, 4
%4 = mul i64 %3, 2
%baseInt = ptrtoint ptr %base to i64
%add1 = add i64 %baseInt, %2
%add2 = add i64 %baseInt, %4
%addr1 = inttoptr i64 %add1 to ptr
%addr2 = inttoptr i64 %add2 to ptr
store i16 %r, ptr %addr1, align 2
store i16 %r, ptr %addr2, align 2
ret void
}
define void @stride_var(i32 %a, ptr %base, i16 %r, i64 %n) {
; Reuse add1 to compute add2 to save a add.s64
; CHECK-LABEL: @stride_var(
; CHECK-NEXT: [[I1:%.*]] = sext i32 [[A:%.*]] to i64
; CHECK-NEXT: [[I2:%.*]] = mul i64 [[I1]], 2
; CHECK-NEXT: [[BI:%.*]] = ptrtoint ptr [[BASE:%.*]] to i64
; CHECK-NEXT: [[ADD1:%.*]] = add i64 [[BI]], [[I2]]
; CHECK-NEXT: [[TMP3:%.*]] = shl i64 [[N:%.*]], 1
; CHECK-NEXT: [[ADD2:%.*]] = add i64 [[ADD1]], [[TMP3]]
; CHECK-NEXT: [[ADDR1:%.*]] = inttoptr i64 [[ADD1]] to ptr
; CHECK-NEXT: [[ADDR2:%.*]] = inttoptr i64 [[ADD2]] to ptr
; CHECK-NEXT: store i16 [[R:%.*]], ptr [[ADDR1]], align 2
; CHECK-NEXT: store i16 [[R]], ptr [[ADDR2]], align 2
; CHECK-NEXT: ret void
;
%1 = sext i32 %a to i64
%2 = mul i64 %1, 2
%3 = add i64 %1, %n
%4 = mul i64 %3, 2
%baseInt = ptrtoint ptr %base to i64
%add1 = add i64 %baseInt, %2
%add2 = add i64 %baseInt, %4
%addr1 = inttoptr i64 %add1 to ptr
%addr2 = inttoptr i64 %add2 to ptr
store i16 %r, ptr %addr1, align 2
store i16 %r, ptr %addr2, align 2
ret void
}
; Base Delta
define void @base_const(i32 %a, ptr %base, i16 %r) {
; Reuse add1 to compute add2
; CHECK-LABEL: @base_const(
; CHECK-NEXT: [[I1:%.*]] = sext i32 [[A:%.*]] to i64
; CHECK-NEXT: [[I2:%.*]] = mul i64 [[I1]], 2
; CHECK-NEXT: [[BI:%.*]] = ptrtoint ptr [[BASE:%.*]] to i64
; CHECK-NEXT: [[ADD1:%.*]] = add i64 [[BI]], [[I2]]
; CHECK-NEXT: [[ADD2:%.*]] = add i64 [[ADD1]], 5
; CHECK-NEXT: [[ADDR1:%.*]] = inttoptr i64 [[ADD1]] to ptr
; CHECK-NEXT: [[ADDR2:%.*]] = inttoptr i64 [[ADD2]] to ptr
; CHECK-NEXT: store i16 [[R:%.*]], ptr [[ADDR1]], align 2
; CHECK-NEXT: store i16 [[R]], ptr [[ADDR2]], align 2
; CHECK-NEXT: ret void
;
%1 = sext i32 %a to i64
%2 = mul i64 %1, 2
%baseInt = ptrtoint ptr %base to i64
%add1 = add i64 %baseInt, %2
%add2.0 = add i64 %baseInt, 5
%add2 = add i64 %add2.0, %2
%addr1 = inttoptr i64 %add1 to ptr
%addr2 = inttoptr i64 %add2 to ptr
store i16 %r, ptr %addr1, align 2
store i16 %r, ptr %addr2, align 2
ret void
}
define void @base_var(i32 %a, ptr %base, i16 %r, i64 %n) {
; Reuse add1 to compute add2
; CHECK-LABEL: @base_var(
; CHECK-NEXT: [[I1:%.*]] = sext i32 [[A:%.*]] to i64
; CHECK-NEXT: [[I2:%.*]] = mul i64 [[I1]], 2
; CHECK-NEXT: [[BI:%.*]] = ptrtoint ptr [[BASE:%.*]] to i64
; CHECK-NEXT: [[ADD1:%.*]] = add i64 [[BI]], [[I2]]
; CHECK-NEXT: [[ADD2:%.*]] = add i64 [[ADD1]], [[N:%.*]]
; CHECK-NEXT: [[ADDR1:%.*]] = inttoptr i64 [[ADD1]] to ptr
; CHECK-NEXT: [[ADDR2:%.*]] = inttoptr i64 [[ADD2]] to ptr
; CHECK-NEXT: store i16 [[R:%.*]], ptr [[ADDR1]], align 2
; CHECK-NEXT: store i16 [[R]], ptr [[ADDR2]], align 2
; CHECK-NEXT: ret void
;
%1 = sext i32 %a to i64
%2 = mul i64 %1, 2
%baseInt = ptrtoint ptr %base to i64
%add1 = add i64 %baseInt, %2
%add2.0 = add i64 %baseInt, %n
%add2 = add i64 %add2.0, %2
%addr1 = inttoptr i64 %add1 to ptr
%addr2 = inttoptr i64 %add2 to ptr
store i16 %r, ptr %addr1, align 2
store i16 %r, ptr %addr2, align 2
ret void
}
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