7f107c3019
While sinking instructions (that are loop invariant) from preheader to the exit block, we are skipping instructions due to decrementing instruction iterator twice.
197 lines
7.3 KiB
LLVM
197 lines
7.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -passes=indvars -S -indvars-predicate-loops=0 < %s | FileCheck %s
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target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
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define i32 @remove_loop(i32 %size) {
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; CHECK-LABEL: define i32 @remove_loop(
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; CHECK-SAME: i32 [[SIZE:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*]]:
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; CHECK-NEXT: br label %[[WHILE_COND:.*]]
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; CHECK: [[WHILE_COND]]:
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; CHECK-NEXT: [[SIZE_ADDR_0:%.*]] = phi i32 [ [[SIZE]], %[[ENTRY]] ], [ [[SUB:%.*]], %[[WHILE_COND]] ]
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; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[SIZE_ADDR_0]], 31
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; CHECK-NEXT: [[SUB]] = add i32 [[SIZE_ADDR_0]], -32
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; CHECK-NEXT: br i1 [[CMP]], label %[[WHILE_COND]], label %[[WHILE_END:.*]]
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; CHECK: [[WHILE_END]]:
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; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[SIZE]], 31
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; CHECK-NEXT: [[UMIN:%.*]] = call i32 @llvm.umin.i32(i32 [[SIZE]], i32 31)
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; CHECK-NEXT: [[TMP1:%.*]] = sub i32 [[TMP0]], [[UMIN]]
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; CHECK-NEXT: [[TMP2:%.*]] = lshr i32 [[TMP1]], 5
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; CHECK-NEXT: [[TMP3:%.*]] = shl nuw i32 [[TMP2]], 5
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; CHECK-NEXT: [[TMP4:%.*]] = sub i32 [[SIZE]], [[TMP3]]
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; CHECK-NEXT: ret i32 [[TMP4]]
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;
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entry:
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br label %while.cond
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while.cond: ; preds = %while.cond, %entry
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%size.addr.0 = phi i32 [ %size, %entry ], [ %sub, %while.cond ]
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%cmp = icmp ugt i32 %size.addr.0, 31
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%sub = add i32 %size.addr.0, -32
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br i1 %cmp, label %while.cond, label %while.end
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while.end: ; preds = %while.cond
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%size.lcssa = phi i32 [ %size.addr.0, %while.cond ]
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ret i32 %size.lcssa
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}
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define i32 @used_loop(i32 %size) minsize {
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; CHECK-LABEL: @used_loop(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[WHILE_COND:%.*]]
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; CHECK: while.cond:
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; CHECK-NEXT: [[SIZE_ADDR_0:%.*]] = phi i32 [ [[SIZE:%.*]], [[ENTRY:%.*]] ], [ [[SUB:%.*]], [[WHILE_COND]] ]
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; CHECK-NEXT: tail call void @call()
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; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[SIZE_ADDR_0]], 31
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; CHECK-NEXT: [[SUB]] = add i32 [[SIZE_ADDR_0]], -32
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; CHECK-NEXT: br i1 [[CMP]], label [[WHILE_COND]], label [[WHILE_END:%.*]]
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; CHECK: while.end:
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; CHECK-NEXT: [[SIZE_LCSSA:%.*]] = phi i32 [ [[SIZE_ADDR_0]], [[WHILE_COND]] ]
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; CHECK-NEXT: ret i32 [[SIZE_LCSSA]]
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;
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entry:
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br label %while.cond
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while.cond: ; preds = %while.cond, %entry
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%size.addr.0 = phi i32 [ %size, %entry ], [ %sub, %while.cond ]
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tail call void @call()
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%cmp = icmp ugt i32 %size.addr.0, 31
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%sub = add i32 %size.addr.0, -32
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br i1 %cmp, label %while.cond, label %while.end
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while.end: ; preds = %while.cond
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%size.lcssa = phi i32 [ %size.addr.0, %while.cond ]
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ret i32 %size.lcssa
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}
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define i32 @test_signed_while(i32 %S) {
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; CHECK-LABEL: @test_signed_while(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[WHILE_COND:%.*]]
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; CHECK: while.cond:
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; CHECK-NEXT: [[S_ADDR_0:%.*]] = phi i32 [ [[S:%.*]], [[ENTRY:%.*]] ], [ [[SUB:%.*]], [[WHILE_BODY:%.*]] ]
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; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[S_ADDR_0]], 31
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; CHECK-NEXT: br i1 [[CMP]], label [[WHILE_BODY]], label [[WHILE_END:%.*]]
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; CHECK: while.body:
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; CHECK-NEXT: [[SUB]] = add nsw i32 [[S_ADDR_0]], -32
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; CHECK-NEXT: tail call void @call()
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; CHECK-NEXT: br label [[WHILE_COND]]
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; CHECK: while.end:
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; CHECK-NEXT: [[S_ADDR_0_LCSSA:%.*]] = phi i32 [ [[S_ADDR_0]], [[WHILE_COND]] ]
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; CHECK-NEXT: ret i32 [[S_ADDR_0_LCSSA]]
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;
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entry:
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br label %while.cond
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while.cond: ; preds = %while.body, %entry
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%S.addr.0 = phi i32 [ %S, %entry ], [ %sub, %while.body ]
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%cmp = icmp sgt i32 %S.addr.0, 31
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br i1 %cmp, label %while.body, label %while.end
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while.body: ; preds = %while.cond
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%sub = add nsw i32 %S.addr.0, -32
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tail call void @call()
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br label %while.cond
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while.end: ; preds = %while.cond
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%S.addr.0.lcssa = phi i32 [ %S.addr.0, %while.cond ]
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ret i32 %S.addr.0.lcssa
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}
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define i32 @test_signed_do(i32 %S) {
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; CHECK-LABEL: @test_signed_do(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[DO_BODY:%.*]]
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; CHECK: do.body:
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; CHECK-NEXT: [[S_ADDR_0:%.*]] = phi i32 [ [[S:%.*]], [[ENTRY:%.*]] ], [ [[SUB:%.*]], [[DO_BODY]] ]
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; CHECK-NEXT: [[SUB]] = add nsw i32 [[S_ADDR_0]], -16
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; CHECK-NEXT: tail call void @call()
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; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[SUB]], 15
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; CHECK-NEXT: br i1 [[CMP]], label [[DO_BODY]], label [[DO_END:%.*]]
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; CHECK: do.end:
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; CHECK-NEXT: [[SUB_LCSSA:%.*]] = phi i32 [ [[SUB]], [[DO_BODY]] ]
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; CHECK-NEXT: ret i32 [[SUB_LCSSA]]
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;
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entry:
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br label %do.body
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do.body: ; preds = %do.body, %entry
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%S.addr.0 = phi i32 [ %S, %entry ], [ %sub, %do.body ]
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%sub = add nsw i32 %S.addr.0, -16
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tail call void @call()
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%cmp = icmp sgt i32 %sub, 15
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br i1 %cmp, label %do.body, label %do.end
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do.end: ; preds = %do.body
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%sub.lcssa = phi i32 [ %sub, %do.body ]
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ret i32 %sub.lcssa
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}
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define i32 @test_unsigned_while(i32 %S) {
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; CHECK-LABEL: @test_unsigned_while(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[WHILE_COND:%.*]]
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; CHECK: while.cond:
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; CHECK-NEXT: [[S_ADDR_0:%.*]] = phi i32 [ [[S:%.*]], [[ENTRY:%.*]] ], [ [[SUB:%.*]], [[WHILE_BODY:%.*]] ]
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; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[S_ADDR_0]], 15
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; CHECK-NEXT: br i1 [[CMP]], label [[WHILE_BODY]], label [[WHILE_END:%.*]]
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; CHECK: while.body:
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; CHECK-NEXT: [[SUB]] = add i32 [[S_ADDR_0]], -16
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; CHECK-NEXT: tail call void @call()
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; CHECK-NEXT: br label [[WHILE_COND]]
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; CHECK: while.end:
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; CHECK-NEXT: [[S_ADDR_0_LCSSA:%.*]] = phi i32 [ [[S_ADDR_0]], [[WHILE_COND]] ]
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; CHECK-NEXT: ret i32 [[S_ADDR_0_LCSSA]]
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;
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entry:
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br label %while.cond
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while.cond: ; preds = %while.body, %entry
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%S.addr.0 = phi i32 [ %S, %entry ], [ %sub, %while.body ]
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%cmp = icmp ugt i32 %S.addr.0, 15
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br i1 %cmp, label %while.body, label %while.end
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while.body: ; preds = %while.cond
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%sub = add i32 %S.addr.0, -16
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tail call void @call()
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br label %while.cond
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while.end: ; preds = %while.cond
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%S.addr.0.lcssa = phi i32 [ %S.addr.0, %while.cond ]
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ret i32 %S.addr.0.lcssa
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}
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define i32 @test_unsigned_do(i32 %S) {
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; CHECK-LABEL: @test_unsigned_do(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[DO_BODY:%.*]]
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; CHECK: do.body:
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; CHECK-NEXT: [[S_ADDR_0:%.*]] = phi i32 [ [[S:%.*]], [[ENTRY:%.*]] ], [ [[SUB:%.*]], [[DO_BODY]] ]
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; CHECK-NEXT: [[SUB]] = add i32 [[S_ADDR_0]], -16
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; CHECK-NEXT: tail call void @call()
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; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[SUB]], 15
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; CHECK-NEXT: br i1 [[CMP]], label [[DO_BODY]], label [[DO_END:%.*]]
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; CHECK: do.end:
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; CHECK-NEXT: [[SUB_LCSSA:%.*]] = phi i32 [ [[SUB]], [[DO_BODY]] ]
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; CHECK-NEXT: ret i32 [[SUB_LCSSA]]
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;
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entry:
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br label %do.body
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do.body: ; preds = %do.body, %entry
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%S.addr.0 = phi i32 [ %S, %entry ], [ %sub, %do.body ]
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%sub = add i32 %S.addr.0, -16
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tail call void @call()
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%cmp = icmp ugt i32 %sub, 15
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br i1 %cmp, label %do.body, label %do.end
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do.end: ; preds = %do.body
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%sub.lcssa = phi i32 [ %sub, %do.body ]
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ret i32 %sub.lcssa
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}
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declare void @call()
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