David Green 73cd3d4391 [LSR] Prevent creating SCEVs of addrecs from mismatching loops ...

LSR can include Regs of AddRec SCEVs from different loops, which do not combine
well when added in Scalar Evolution. As they should never produce constant
differences so we can just guard against trying to create them.

Fixes #60927

2023-02-22 22:50:37 +00:00

..

AggressiveInstCombine

[AggressiveInstCombine] Fix invalid TypeSize conversion when combining loads.

2022-12-17 15:34:27 +00:00

CFGuard

[NFC][TargetParser] Remove llvm/ADT/Triple.h

2023-02-07 12:39:46 +00:00

Coroutines

[NFC] Use single quotes for single char output during printPipline

2023-02-22 02:35:13 +00:00

Hello

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InstCombine

[Assignment Tracking] Choose better passes for RemoveRedundantDbgInstrs call

2023-02-22 16:28:06 +00:00

Instrumentation

[NFC] Use single quotes for single char output during printPipline

2023-02-22 02:35:13 +00:00

IPO

[GlobalOpt] Add struct for parts during GlobalSRA (NFC)

2023-02-22 16:35:10 +01:00

ObjCARC

Lift EHPersonalities from Analysis to IR (NFC)

2023-01-27 18:05:13 +01:00

Scalar

[LSR] Prevent creating SCEVs of addrecs from mismatching loops

2023-02-22 22:50:37 +00:00

Utils

[Local][SimplifyCFG][GVN] Handle !nontemporal in combineMetadata

2023-02-22 14:47:00 +01:00

Vectorize

[Assignment Tracking] Choose better passes for RemoveRedundantDbgInstrs call

2023-02-22 16:28:06 +00:00

CMakeLists.txt

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