74e8f29f31
`weightCalcHelper` is responsible for adding hints to MRI. Prior to this PR, we fell back on register ID as the last tie breaker for sorting hints. However, there is an opportunity to add an additional sorting characteristic: whether or not a register is a callee-saved-register. I thought of this idea because I saw that `AllocationOrder::create` calls `RegisterClassInfo::getOrder`, which returns a list of registers such that the registers which alias callee-saved-registers come last. From this, I conclude that the register allocator prefers an order such that callee-saved-registers are allocated after non-callee-saved-registers to avoid having to spill the CSR. This sorting characteristic occurs only as a tie breaker to the Weight calculation. This is a good idea since the weight calculation is pretty complex and I'm sure it is a pretty stable metric. I think its pretty reasonable to agree that whether a register is callee-saved or not is a better tie breaker than register ID. I think this is evident by the test diff, since the changes all seem to have no impact or improve the register allocation.
103 lines
2.7 KiB
LLVM
103 lines
2.7 KiB
LLVM
; RUN: llc -mtriple=sparc -disable-sparc-leaf-proc=0 < %s | FileCheck %s
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; CHECK-LABEL: func_nobody:
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; CHECK: retl
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; CHECK-NEXT: nop
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define void @func_nobody() {
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entry:
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ret void
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}
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; CHECK-LABEL: return_int_const:
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; CHECK: retl
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; CHECK-NEXT: mov 1729, %o0
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define i32 @return_int_const() {
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entry:
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ret i32 1729
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}
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; CHECK-LABEL: return_double_const:
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; CHECK: sethi
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; CHECK: retl
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; CHECK-NEXT: ldd {{.*}}, %f0
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define double @return_double_const() {
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entry:
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ret double 0.000000e+00
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}
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; CHECK-LABEL: leaf_proc_with_args:
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; CHECK: add {{%o[0-1]}}, {{%o[0-1]}}, [[R:%[go][0-7]]]
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; CHECK: retl
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; CHECK-NEXT: add [[R]], %o2, %o0
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define i32 @leaf_proc_with_args(i32 %a, i32 %b, i32 %c) {
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entry:
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%0 = add nsw i32 %b, %a
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%1 = add nsw i32 %0, %c
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ret i32 %1
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}
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; CHECK-LABEL: leaf_proc_with_args_in_stack:
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; CHECK-DAG: ld [%sp+92], {{%[go][0-7]}}
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; CHECK-DAG: ld [%sp+96], {{%[go][0-7]}}
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; CHECK: retl
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; CHECK-NEXT: add {{.*}}, %o0
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define i32 @leaf_proc_with_args_in_stack(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h) {
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entry:
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%0 = add nsw i32 %b, %a
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%1 = add nsw i32 %0, %c
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%2 = add nsw i32 %1, %d
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%3 = add nsw i32 %2, %e
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%4 = add nsw i32 %3, %f
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%5 = add nsw i32 %4, %g
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%6 = add nsw i32 %5, %h
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ret i32 %6
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}
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; CHECK-LABEL: leaf_proc_with_local_array:
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; CHECK: add %sp, -104, %sp
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; CHECK: mov 1, [[R1:%[go][0-7]]]
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; CHECK: st [[R1]], [%sp+96]
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; CHECK: mov 2, [[R2:%[go][0-7]]]
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; CHECK: st [[R2]], [%sp+100]
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; CHECK: ld {{.+}}, %o0
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; CHECK: retl
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; CHECK-NEXT: add %sp, 104, %sp
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define i32 @leaf_proc_with_local_array(i32 %a, i32 %b, i32 %c) {
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entry:
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%array = alloca [2 x i32], align 4
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%0 = sub nsw i32 %b, %c
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%1 = getelementptr inbounds [2 x i32], ptr %array, i32 0, i32 0
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store i32 1, ptr %1, align 4
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%2 = getelementptr inbounds [2 x i32], ptr %array, i32 0, i32 1
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store i32 2, ptr %2, align 4
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%3 = getelementptr inbounds [2 x i32], ptr %array, i32 0, i32 %a
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%4 = load i32, ptr %3, align 4
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ret i32 %4
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}
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; Here we have a leaf function where it contains inline assembly, which means
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; that register renumbering might interfere with the register constraints.
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; As a result the function is not marked as being a leaf one.
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; CHECK-LABEL: leaf_proc_give_up
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; CHECK: save %sp, -96, %sp
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; CHECK: ld [%fp+92], %o5
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; CHECK: mov %i5, %o4
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; CHECK: mov %i4, %o3
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; CHECK: mov %i3, %o2
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; CHECK: mov %i2, %o1
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; CHECK: mov %i1, %o0
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; CHECK: mov %i0, %g1
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; CHECK: ret
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; CHECK-NEXT: restore %g0, %o0, %o0
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define i32 @leaf_proc_give_up(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4, i32 %5, i32 %6) {
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Entry:
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%g = call i32 asm sideeffect "", "={o0},{g1},{o0},{o1},{o2},{o3},{o4},{o5}"(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4, i32 %5, i32 %6)
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ret i32 %g
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}
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