9df924a634
A new register class as well as a number of related subregisters are being added to Future CPU. These registers are Dense Math Registers (DMR) and are 1024 bits long. These regsiters can also be used in consecutive pairs which leads to a register that is 2048 bits. This patch also adds 7 new instructions that use these registers. More instructions will be added in future patches. Reviewed By: amyk, saghir Differential Revision: https://reviews.llvm.org/D136366
15 lines
500 B
TableGen
15 lines
500 B
TableGen
//===-- PPCInstrFuture.td - Future Instruction Set --------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the instructions introduced for the Future CPU.
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//
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//===----------------------------------------------------------------------===//
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