75bb30ddbf
The previous position of llvm.protected.field.ptr lowering for loads and stores was problematic as it not only inhibited optimizations such as DSE (as stores to a llvm.protected.field.ptr were not considered to must-alias stores to the non-protected.field pointer) but also required changes to other optimization passes to avoid transformations that would reduce PFP coverage. Address this by moving the load/store part of the lowering to InstCombine, where it will run earlier than the PFP-breaking and AA-relying transformations. The deactivation symbol, null comparison and EmuPAC parts of the lowering remain in PreISelLowering. Now that the transformation inhibitions are no longer needed, remove them (i.e. partially revert #151649, and revert #182976). This change resulted in a 2.4% reduction in Fleetbench .text size and the following improvements to PFP performance overhead for BM_PROTO_Arena on various microarchitectures: before after Apple M2 Ultra 3.5% 3.3% Google Axion C4A 3.3% 2.9% Google Axion N4A 2.7% 2.2% Reviewers: fmayer, nikic, vitalybuka Reviewed By: fmayer Pull Request: https://github.com/llvm/llvm-project/pull/186548
62 lines
2.8 KiB
LLVM
62 lines
2.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
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; RUN: opt -passes=instcombine -S < %s | FileCheck %s
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@ds1 = external global i8
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@ds2 = external global i8
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define ptr @load_hw(ptr addrspace(1) %ptrptr) {
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; CHECK-LABEL: define ptr @load_hw(
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; CHECK-SAME: ptr addrspace(1) [[PTRPTR:%.*]]) {
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; CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr addrspace(1) [[PTRPTR]], align 8
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; CHECK-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[TMP1]] to i64
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; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.ptrauth.auth(i64 [[TMP2]], i32 2, i64 1)
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; CHECK-NEXT: [[PTR:%.*]] = inttoptr i64 [[TMP3]] to ptr
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; CHECK-NEXT: ret ptr [[PTR]]
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;
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%protptrptr = call ptr addrspace(1) @llvm.protected.field.ptr.p1(ptr addrspace(1) %ptrptr, i64 1, i1 true)
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%ptr = load ptr, ptr addrspace(1) %protptrptr
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ret ptr %ptr
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}
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define void @store_hw(ptr addrspace(1) %ptrptr, ptr %ptr) {
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; CHECK-LABEL: define void @store_hw(
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; CHECK-SAME: ptr addrspace(1) [[PTRPTR:%.*]], ptr [[PTR:%.*]]) {
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; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[PTR]] to i64
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; CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.ptrauth.sign(i64 [[TMP1]], i32 2, i64 2)
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; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr
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; CHECK-NEXT: store ptr [[TMP3]], ptr addrspace(1) [[PTRPTR]], align 8
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; CHECK-NEXT: ret void
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;
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%protptrptr = call ptr addrspace(1) @llvm.protected.field.ptr.p1(ptr addrspace(1) %ptrptr, i64 2, i1 true)
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store ptr %ptr, ptr addrspace(1) %protptrptr
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ret void
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}
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define ptr @load_hw_ds(ptr addrspace(1) %ptrptr) {
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; CHECK-LABEL: define ptr @load_hw_ds(
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; CHECK-SAME: ptr addrspace(1) [[PTRPTR:%.*]]) {
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; CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr addrspace(1) [[PTRPTR]], align 8
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; CHECK-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[TMP1]] to i64
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; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.ptrauth.auth(i64 [[TMP2]], i32 2, i64 1) [ "deactivation-symbol"(ptr @ds1) ]
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; CHECK-NEXT: [[PTR:%.*]] = inttoptr i64 [[TMP3]] to ptr
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; CHECK-NEXT: ret ptr [[PTR]]
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;
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%protptrptr = call ptr addrspace(1) @llvm.protected.field.ptr.p1(ptr addrspace(1) %ptrptr, i64 1, i1 true) [ "deactivation-symbol"(ptr @ds1) ]
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%ptr = load ptr, ptr addrspace(1) %protptrptr
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ret ptr %ptr
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}
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define void @store_hw_ds(ptr addrspace(1) %ptrptr, ptr %ptr) {
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; CHECK-LABEL: define void @store_hw_ds(
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; CHECK-SAME: ptr addrspace(1) [[PTRPTR:%.*]], ptr [[PTR:%.*]]) {
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; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[PTR]] to i64
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; CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.ptrauth.sign(i64 [[TMP1]], i32 2, i64 2) [ "deactivation-symbol"(ptr @ds2) ]
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; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr
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; CHECK-NEXT: store ptr [[TMP3]], ptr addrspace(1) [[PTRPTR]], align 8
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; CHECK-NEXT: ret void
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;
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%protptrptr = call ptr addrspace(1) @llvm.protected.field.ptr.p1(ptr addrspace(1) %ptrptr, i64 2, i1 true) [ "deactivation-symbol"(ptr @ds2) ]
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store ptr %ptr, ptr addrspace(1) %protptrptr
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ret void
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}
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