ddf5e86c22
r361845 changed the way we handle "D16" vs. "D32" targets; there used to be a negative "d16" which removed instructions from the instruction set, and now there's a "d32" feature which adds instructions to the instruction set. This is good, but there was an oversight in the implementation: the behavior of VFPv2 was changed. In particular, the "vfp2" feature was changed to imply "d32". This is wrong: VFPv2 only supports 16 D registers. In practice, this means if you specify -mfpu=vfpv2, the compiler will generate illegal instructions. This patch gets rid of "vfp2d16" and "vfp2d16sp", and fixes "vfp2" and "vfp2sp" so they don't imply "d32". Differential Revision: https://reviews.llvm.org/D67375 llvm-svn: 372186
47 lines
2.1 KiB
LLVM
47 lines
2.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=thumbv7em-arm-none-eabi < %s | FileCheck %s
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target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
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target triple = "thumbv7em-arm-none-eabi"
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@a = hidden global i32 0, align 4
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define hidden void @fn1() nounwind #0 {
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; CHECK-LABEL: fn1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r7, lr}
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; CHECK-NEXT: push {r7, lr}
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; CHECK-NEXT: vldr d0, .LCPI0_0
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; CHECK-NEXT: vmov r0, r1, d0
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; CHECK-NEXT: mov r2, r0
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; CHECK-NEXT: mov r3, r1
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; CHECK-NEXT: bl __aeabi_dcmpeq
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; CHECK-NEXT: cbnz r0, .LBB0_2
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; CHECK-NEXT: b .LBB0_1
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; CHECK-NEXT: .LBB0_1: @ %land.rhs
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; CHECK-NEXT: b .LBB0_2
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; CHECK-NEXT: .LBB0_2: @ %land.end
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; CHECK-NEXT: pop {r7, pc}
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; CHECK-NEXT: .p2align 3
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; CHECK-NEXT: @ %bb.3:
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; CHECK-NEXT: .LCPI0_0:
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; CHECK-NEXT: .long 0 @ double 0
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; CHECK-NEXT: .long 0
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entry:
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%0 = load i32, i32* @a, align 4
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%conv = sitofp i32 %0 to double
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%mul = fmul nnan ninf nsz double 0.000000e+00, %conv
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%tobool = fcmp nnan ninf nsz une double %mul, 0.000000e+00
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br i1 %tobool, label %land.rhs, label %land.end
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land.rhs: ; preds = %entry
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br label %land.end
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land.end: ; preds = %land.rhs, %entry
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%1 = phi i1 [ false, %entry ], [ false, %land.rhs ]
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%land.ext = zext i1 %1 to i32
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ret void
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}
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attributes #0 = { noinline nounwind optnone "correctly-rounded-divide-sqrt-fp-math"="false" "denormal-fp-math"="preserve-sign" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="true" "no-jump-tables"="false" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-m4" "target-features"="+armv7e-m,+dsp,+fp16,+fpregs,+hwdiv,+thumb-mode,+vfp2sp,+vfp3d16sp,+vfp4d16sp,-aes,-crc,-crypto,-dotprod,-fp16fml,-fullfp16,-hwdiv-arm,-lob,-mve,-mve.fp,-ras,-sb,-sha2" "unsafe-fp-math"="false" "use-soft-float"="false" }
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