76e14deb4a
BreakFalseDeps picks the best register for undef operands if instructions have false dependency. The problem is if the instruction is close to the beginning of the function, ReachingDefAnalysis is over optimism to the unused registers, which results in collision with registers just defined in the caller. This patch changes the selection of undef register in an reverse order, which reduces the probability of register collisions between caller and callee. It brings improvement in some of our internal benchmarks with negligible effect on other benchmarks.
157 lines
4.8 KiB
LLVM
157 lines
4.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=x86_64-unknown-unknown -mcpu=generic -mattr=+avx512f -fast-isel --fast-isel-abort=1 < %s | FileCheck %s --check-prefix=AVX
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; RUN: llc -verify-machineinstrs -mtriple=i686-unknown-unknown -mcpu=generic -mattr=+avx512f -fast-isel --fast-isel-abort=1 < %s | FileCheck %s --check-prefix=AVX_X86
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define double @int_to_double_rr(i32 %a) {
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; AVX-LABEL: int_to_double_rr:
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; AVX: # %bb.0: # %entry
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; AVX-NEXT: vcvtusi2sd %edi, %xmm15, %xmm0
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; AVX-NEXT: retq
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;
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; AVX_X86-LABEL: int_to_double_rr:
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; AVX_X86: # %bb.0: # %entry
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; AVX_X86-NEXT: pushl %ebp
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; AVX_X86-NEXT: .cfi_def_cfa_offset 8
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; AVX_X86-NEXT: .cfi_offset %ebp, -8
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; AVX_X86-NEXT: movl %esp, %ebp
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; AVX_X86-NEXT: .cfi_def_cfa_register %ebp
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; AVX_X86-NEXT: andl $-8, %esp
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; AVX_X86-NEXT: subl $8, %esp
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; AVX_X86-NEXT: vcvtusi2sdl 8(%ebp), %xmm7, %xmm0
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; AVX_X86-NEXT: vmovsd %xmm0, (%esp)
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; AVX_X86-NEXT: fldl (%esp)
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; AVX_X86-NEXT: movl %ebp, %esp
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; AVX_X86-NEXT: popl %ebp
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; AVX_X86-NEXT: .cfi_def_cfa %esp, 4
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; AVX_X86-NEXT: retl
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entry:
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%0 = uitofp i32 %a to double
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ret double %0
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}
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define double @int_to_double_rm(ptr %a) {
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; AVX-LABEL: int_to_double_rm:
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; AVX: # %bb.0: # %entry
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; AVX-NEXT: vcvtusi2sdl (%rdi), %xmm15, %xmm0
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; AVX-NEXT: retq
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;
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; AVX_X86-LABEL: int_to_double_rm:
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; AVX_X86: # %bb.0: # %entry
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; AVX_X86-NEXT: pushl %ebp
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; AVX_X86-NEXT: .cfi_def_cfa_offset 8
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; AVX_X86-NEXT: .cfi_offset %ebp, -8
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; AVX_X86-NEXT: movl %esp, %ebp
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; AVX_X86-NEXT: .cfi_def_cfa_register %ebp
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; AVX_X86-NEXT: andl $-8, %esp
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; AVX_X86-NEXT: subl $8, %esp
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; AVX_X86-NEXT: movl 8(%ebp), %eax
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; AVX_X86-NEXT: vcvtusi2sdl (%eax), %xmm7, %xmm0
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; AVX_X86-NEXT: vmovsd %xmm0, (%esp)
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; AVX_X86-NEXT: fldl (%esp)
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; AVX_X86-NEXT: movl %ebp, %esp
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; AVX_X86-NEXT: popl %ebp
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; AVX_X86-NEXT: .cfi_def_cfa %esp, 4
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; AVX_X86-NEXT: retl
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entry:
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%0 = load i32, ptr %a
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%1 = uitofp i32 %0 to double
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ret double %1
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}
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define double @int_to_double_rm_optsize(ptr %a) optsize {
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; AVX-LABEL: int_to_double_rm_optsize:
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; AVX: # %bb.0: # %entry
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; AVX-NEXT: vcvtusi2sdl (%rdi), %xmm15, %xmm0
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; AVX-NEXT: retq
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;
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; AVX_X86-LABEL: int_to_double_rm_optsize:
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; AVX_X86: # %bb.0: # %entry
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; AVX_X86-NEXT: pushl %ebp
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; AVX_X86-NEXT: .cfi_def_cfa_offset 8
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; AVX_X86-NEXT: .cfi_offset %ebp, -8
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; AVX_X86-NEXT: movl %esp, %ebp
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; AVX_X86-NEXT: .cfi_def_cfa_register %ebp
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; AVX_X86-NEXT: andl $-8, %esp
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; AVX_X86-NEXT: subl $8, %esp
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; AVX_X86-NEXT: movl 8(%ebp), %eax
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; AVX_X86-NEXT: vcvtusi2sdl (%eax), %xmm7, %xmm0
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; AVX_X86-NEXT: vmovsd %xmm0, (%esp)
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; AVX_X86-NEXT: fldl (%esp)
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; AVX_X86-NEXT: movl %ebp, %esp
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; AVX_X86-NEXT: popl %ebp
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; AVX_X86-NEXT: .cfi_def_cfa %esp, 4
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; AVX_X86-NEXT: retl
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entry:
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%0 = load i32, ptr %a
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%1 = uitofp i32 %0 to double
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ret double %1
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}
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define float @int_to_float_rr(i32 %a) {
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; AVX-LABEL: int_to_float_rr:
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; AVX: # %bb.0: # %entry
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; AVX-NEXT: vcvtusi2ss %edi, %xmm15, %xmm0
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; AVX-NEXT: retq
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;
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; AVX_X86-LABEL: int_to_float_rr:
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; AVX_X86: # %bb.0: # %entry
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; AVX_X86-NEXT: pushl %eax
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; AVX_X86-NEXT: .cfi_def_cfa_offset 8
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; AVX_X86-NEXT: vcvtusi2ssl {{[0-9]+}}(%esp), %xmm7, %xmm0
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; AVX_X86-NEXT: vmovss %xmm0, (%esp)
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; AVX_X86-NEXT: flds (%esp)
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; AVX_X86-NEXT: popl %eax
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; AVX_X86-NEXT: .cfi_def_cfa_offset 4
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; AVX_X86-NEXT: retl
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entry:
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%0 = uitofp i32 %a to float
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ret float %0
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}
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define float @int_to_float_rm(ptr %a) {
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; AVX-LABEL: int_to_float_rm:
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; AVX: # %bb.0: # %entry
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; AVX-NEXT: vcvtusi2ssl (%rdi), %xmm15, %xmm0
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; AVX-NEXT: retq
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;
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; AVX_X86-LABEL: int_to_float_rm:
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; AVX_X86: # %bb.0: # %entry
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; AVX_X86-NEXT: pushl %eax
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; AVX_X86-NEXT: .cfi_def_cfa_offset 8
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; AVX_X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; AVX_X86-NEXT: vcvtusi2ssl (%eax), %xmm7, %xmm0
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; AVX_X86-NEXT: vmovss %xmm0, (%esp)
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; AVX_X86-NEXT: flds (%esp)
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; AVX_X86-NEXT: popl %eax
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; AVX_X86-NEXT: .cfi_def_cfa_offset 4
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; AVX_X86-NEXT: retl
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entry:
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%0 = load i32, ptr %a
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%1 = uitofp i32 %0 to float
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ret float %1
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}
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define float @int_to_float_rm_optsize(ptr %a) optsize {
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; AVX-LABEL: int_to_float_rm_optsize:
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; AVX: # %bb.0: # %entry
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; AVX-NEXT: vcvtusi2ssl (%rdi), %xmm15, %xmm0
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; AVX-NEXT: retq
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;
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; AVX_X86-LABEL: int_to_float_rm_optsize:
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; AVX_X86: # %bb.0: # %entry
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; AVX_X86-NEXT: pushl %eax
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; AVX_X86-NEXT: .cfi_def_cfa_offset 8
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; AVX_X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; AVX_X86-NEXT: vcvtusi2ssl (%eax), %xmm7, %xmm0
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; AVX_X86-NEXT: vmovss %xmm0, (%esp)
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; AVX_X86-NEXT: flds (%esp)
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; AVX_X86-NEXT: popl %eax
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; AVX_X86-NEXT: .cfi_def_cfa_offset 4
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; AVX_X86-NEXT: retl
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entry:
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%0 = load i32, ptr %a
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%1 = uitofp i32 %0 to float
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ret float %1
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}
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