76e14deb4a
BreakFalseDeps picks the best register for undef operands if instructions have false dependency. The problem is if the instruction is close to the beginning of the function, ReachingDefAnalysis is over optimism to the unused registers, which results in collision with registers just defined in the caller. This patch changes the selection of undef register in an reverse order, which reduces the probability of register collisions between caller and callee. It brings improvement in some of our internal benchmarks with negligible effect on other benchmarks.
48 lines
1.7 KiB
LLVM
48 lines
1.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mcpu=skylake-avx512 -mtriple=x86_64-unknown-unknown | FileCheck %s
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@b = dso_local local_unnamed_addr global i32 0, align 4
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@c = dso_local local_unnamed_addr global i32 0, align 4
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@d = dso_local local_unnamed_addr global float 0.000000e+00, align 4
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define dso_local float @_Z3fn2v() {
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; CHECK-LABEL: _Z3fn2v:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: pushq %rax
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: callq _Z1av@PLT
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; CHECK-NEXT: # kill: def $al killed $al def $eax
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; CHECK-NEXT: kmovd %eax, %k1
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; CHECK-NEXT: vmovss {{.*#+}} xmm0 {%k1} {z} = [7.5E-1,0.0E+0,0.0E+0,0.0E+0]
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; CHECK-NEXT: cmpl $0, c(%rip)
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; CHECK-NEXT: je .LBB0_2
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; CHECK-NEXT: # %bb.1: # %if.then
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; CHECK-NEXT: vcvtsi2ssl b(%rip), %xmm15, %xmm1
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; CHECK-NEXT: kmovd %eax, %k1
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; CHECK-NEXT: vxorps %xmm2, %xmm2, %xmm2
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; CHECK-NEXT: vmovss %xmm2, %xmm1, %xmm1 {%k1}
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; CHECK-NEXT: vmovss %xmm1, d(%rip)
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; CHECK-NEXT: .LBB0_2: # %if.end
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; CHECK-NEXT: popq %rax
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; CHECK-NEXT: .cfi_def_cfa_offset 8
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; CHECK-NEXT: retq
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entry:
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%call = tail call zeroext i1 @_Z1av()
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%cond = select i1 %call, float 7.500000e-01, float 0.000000e+00
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%0 = load i32, ptr @c, align 4
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%tobool2 = icmp eq i32 %0, 0
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br i1 %tobool2, label %if.end, label %if.then
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if.then: ; preds = %entry
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%1 = load i32, ptr @b, align 4
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%2 = sitofp i32 %1 to float
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%conv5 = select i1 %call, float 0.000000e+00, float %2
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store float %conv5, ptr @d, align 4
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br label %if.end
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if.end: ; preds = %entry, %if.then
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ret float %cond
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}
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declare zeroext i1 @_Z1av()
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