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llvm-project/llvm/lib/Target/RISCV
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Craig Topper 8bde5f06a1 [RISCV] Replace && with ||. Spotted by coverity. 
We should be exiting when the shift amount is greater than
the bit width regardless of whether it is a power of 2.

Reported by Simon Pilgrim here https://reviews.llvm.org/D96661

This requires getting a shift amount that is out of bounds that
wasn't already optimized by SelectionDAG. This would be pretty
trick to construct a test for.

Or it would require a non-power of 2 shift amount and a mask
that has runs of ones and zeros of the next lowest power of 2 from
that shift amount. I tried a little to produce a test for this,
but didn't get it to work.
2021-06-06 13:09:51 -07:00
..
AsmParser
RISCV: add a few deprecated aliases for CSRs
2021-05-21 13:52:58 -07:00
Disassembler
[RISCV] Fix shared libs build
2021-02-09 06:14:25 -06:00
MCTargetDesc
Fix "not all control paths return a value" MSVC warning. NFCI.
2021-06-05 19:42:00 +01:00
TargetInfo
…
CMakeLists.txt
[RISCV] Add a vsetvli insert pass that can be extended to be aware of incoming VL/VTYPE from other basic blocks.
2021-05-24 11:47:27 -07:00
RISCV.h
[RISCV] Add a vsetvli insert pass that can be extended to be aware of incoming VL/VTYPE from other basic blocks.
2021-05-24 11:47:27 -07:00
RISCV.td
[RISCV][NFC] Fix formatting
2021-04-09 14:41:09 +08:00
RISCVAsmPrinter.cpp
[RISCV][NFC] Don't need to create a new STI in RISCVAsmPrinter.
2021-05-10 09:33:23 +08:00
RISCVCallingConv.td
…
RISCVCallLowering.cpp
…
RISCVCallLowering.h
…
RISCVExpandAtomicPseudoInsts.cpp
…
RISCVExpandPseudoInsts.cpp
[RISCV] Add a vsetvli insert pass that can be extended to be aware of incoming VL/VTYPE from other basic blocks.
2021-05-24 11:47:27 -07:00
RISCVFrameLowering.cpp
[RISCV] Reserve an emergency spill slot for any RVV spills
2021-06-03 10:44:34 +01:00
RISCVFrameLowering.h
[RISCV] Fix offset computation for RVV
2021-03-29 17:03:49 +00:00
RISCVInsertVSETVLI.cpp
[RISCV] Teach vsetvli insertion pass that operations on masks don't care about SEW/LMUL.
2021-06-04 09:17:46 -07:00
RISCVInstrFormats.td
[RISCV] Cleanup instruction formats used for B extension ternary operations.
2021-05-06 08:59:05 -07:00
RISCVInstrFormatsC.td
…
RISCVInstrFormatsV.td
[RISCV] Add new vector instructions in v0.10.
2021-02-03 13:28:58 +08:00
RISCVInstrInfo.cpp
[RISCV] Reserve an emergency spill slot for any RVV spills
2021-06-03 10:44:34 +01:00
RISCVInstrInfo.h
[RISCV] Reserve an emergency spill slot for any RVV spills
2021-06-03 10:44:34 +01:00
RISCVInstrInfo.td
[RISCV] Replace AddiPair ComplexPattern with a PatLeaf. NFC
2021-05-16 12:17:52 -07:00
RISCVInstrInfoA.td
[RISCV][NFC] Add explicit type i64 to RV64 only patterns.
2021-04-09 09:37:04 +08:00
RISCVInstrInfoB.td
[RISCV] Optimize xor/or with immediate in the zbs extension
2021-05-25 14:14:09 +08:00
RISCVInstrInfoC.td
[RISCV] Rename WriteShift/ReadShift scheduler classes to WriteShiftImm/ReadShiftImm. Move variable shifts from WriteIALU/ReadIALU to new WriteShiftReg/ReadShiftReg.
2021-03-19 20:39:49 -07:00
RISCVInstrInfoD.td
[RISCV] Cleanup instruction formats used for B extension ternary operations.
2021-05-06 08:59:05 -07:00
RISCVInstrInfoF.td
[RISCV] Cleanup instruction formats used for B extension ternary operations.
2021-05-06 08:59:05 -07:00
RISCVInstrInfoM.td
[RISCV] Add custom type legalization to form MULHSU when possible.
2021-04-01 10:15:55 -07:00
RISCVInstrInfoV.td
[RISCV] Temporary in vmsge(u).vx pseudo instructions can't be V0.
2021-04-21 14:50:29 -07:00
RISCVInstrInfoVPseudos.td
[RISCV] Replace (XLenVT (VLOp GPR:$vl)) with VLOpFrag
2021-06-05 12:49:31 +08:00
RISCVInstrInfoVSDPatterns.td
[RISCV] Minor vector instruction tablegen cleanup. NFC
2021-05-06 11:23:59 -07:00
RISCVInstrInfoVVLPatterns.td
[RISCV] Add octuple to LMULInfo tablegen class, remove octuple_from_str. NFCI
2021-05-28 11:53:05 -07:00
RISCVInstrInfoZfh.td
[RISCV] Cleanup instruction formats used for B extension ternary operations.
2021-05-06 08:59:05 -07:00
RISCVInstructionSelector.cpp
…
RISCVISelDAGToDAG.cpp
[RISCV] Teach vsetvli insertion pass that operations on masks don't care about SEW/LMUL.
2021-06-04 09:17:46 -07:00
RISCVISelDAGToDAG.h
[RISCV] Optimize SEW=64 shifts by splat on RV32.
2021-05-26 10:23:32 -07:00
RISCVISelLowering.cpp
[RISCV] Replace && with ||. Spotted by coverity.
2021-06-06 13:09:51 -07:00
RISCVISelLowering.h
[TargetLowering] Use IRBuilderBase instead of IRBuilder<> (NFC)
2021-06-06 16:29:50 +02:00
RISCVLegalizerInfo.cpp
[globalisel][legalizer] Separate the deprecated LegalizerInfo from the current one
2021-06-01 13:23:48 -07:00
RISCVLegalizerInfo.h
…
RISCVMachineFunctionInfo.h
[RISCV] Don't emit save-restore call if function is a interrupt handler
2021-04-16 12:54:47 +08:00
RISCVMCInstLower.cpp
[RISCV] Move instruction information into the RISCVII namespace (NFC)
2021-05-11 16:32:42 -05:00
RISCVMergeBaseOffset.cpp
…
RISCVRegisterBankInfo.cpp
…
RISCVRegisterBankInfo.h
…
RISCVRegisterBanks.td
…
RISCVRegisterInfo.cpp
[RISCV] Reserve an emergency spill slot for any RVV spills
2021-06-03 10:44:34 +01:00
RISCVRegisterInfo.h
[RISCV] Improve register allocation around vector masks
2021-02-20 14:47:51 +00:00
RISCVRegisterInfo.td
[RISCV] Introduce floating point control and state registers
2021-04-21 12:55:30 +07:00
RISCVSchedRocket.td
[RISCV] Add UnsupportedSchedZfh multiclass to reduce duplicate lines from RISCVSchedRocket.td and RISCVSchedSiFive7.td. NFC
2021-03-31 15:06:14 -07:00
RISCVSchedSiFive7.td
[RISCV] Add UnsupportedSchedZfh multiclass to reduce duplicate lines from RISCVSchedRocket.td and RISCVSchedSiFive7.td. NFC
2021-03-31 15:06:14 -07:00
RISCVSchedule.td
[RISCV] Add UnsupportedSchedZfh multiclass to reduce duplicate lines from RISCVSchedRocket.td and RISCVSchedSiFive7.td. NFC
2021-03-31 15:06:14 -07:00
RISCVScheduleB.td
[RISCV] Move scheduling resources for B into a separate file (NFC)
2021-03-29 20:37:22 -05:00
RISCVSubtarget.cpp
[RISCV] Move getLMULForFixedLengthVector out of RISCVSubtarget.
2021-04-23 15:06:20 -07:00
RISCVSubtarget.h
[RISCV] Enable interleaved vectorization for RVV
2021-05-29 11:03:27 +08:00
RISCVSystemOperands.td
RISCV: add a few deprecated aliases for CSRs
2021-05-21 13:52:58 -07:00
RISCVTargetMachine.cpp
[RISCV] Add a vsetvli insert pass that can be extended to be aware of incoming VL/VTYPE from other basic blocks.
2021-05-24 11:47:27 -07:00
RISCVTargetMachine.h
…
RISCVTargetObjectFile.cpp
ELF: Create unique SHF_GNU_RETAIN sections for llvm.used global objects
2021-02-26 16:38:44 -08:00
RISCVTargetObjectFile.h
…
RISCVTargetTransformInfo.cpp
[RISCV] Add support for fmin/fmax vector reductions
2021-05-03 10:33:51 +01:00
RISCVTargetTransformInfo.h
[RISCV] Expand unaligned fixed-length vector memory accesses
2021-06-02 09:27:44 +01:00