
I regularly struggle reproducing failures in greedy due to changes in priority when resuming the allocation from MIR vs. a complete compilation starting at IR. That is, the fix in e0919b189bf2df4f97f22ba40260ab5153988b14 did not really fix the problem of the instruction distance mattering. Add a way to bypass all of the priority heuristics for MIR tests, by prioritizing only by virtual register number. Could also give this a more specific name, like PrioritizeLowVirtRegNumber
146 lines
5.4 KiB
C++
146 lines
5.4 KiB
C++
//===- RegAllocPriorityAdvisor.cpp - live ranges priority advisor ---------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// Implementation of the default priority advisor and of the Analysis pass.
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//
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//===----------------------------------------------------------------------===//
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#include "RegAllocPriorityAdvisor.h"
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#include "RegAllocGreedy.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/VirtRegMap.h"
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#include "llvm/IR/Module.h"
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#include "llvm/InitializePasses.h"
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#include "llvm/Pass.h"
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using namespace llvm;
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static cl::opt<RegAllocPriorityAdvisorAnalysis::AdvisorMode> Mode(
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"regalloc-enable-priority-advisor", cl::Hidden,
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cl::init(RegAllocPriorityAdvisorAnalysis::AdvisorMode::Default),
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cl::desc("Enable regalloc advisor mode"),
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cl::values(
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clEnumValN(RegAllocPriorityAdvisorAnalysis::AdvisorMode::Default,
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"default", "Default"),
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clEnumValN(RegAllocPriorityAdvisorAnalysis::AdvisorMode::Release,
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"release", "precompiled"),
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clEnumValN(RegAllocPriorityAdvisorAnalysis::AdvisorMode::Development,
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"development", "for training"),
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clEnumValN(
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RegAllocPriorityAdvisorAnalysis::AdvisorMode::Dummy, "dummy",
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"prioritize low virtual register numbers for test and debug")));
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char RegAllocPriorityAdvisorAnalysis::ID = 0;
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INITIALIZE_PASS(RegAllocPriorityAdvisorAnalysis, "regalloc-priority",
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"Regalloc priority policy", false, true)
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namespace {
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class DefaultPriorityAdvisorAnalysis final
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: public RegAllocPriorityAdvisorAnalysis {
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public:
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DefaultPriorityAdvisorAnalysis(bool NotAsRequested)
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: RegAllocPriorityAdvisorAnalysis(AdvisorMode::Default),
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NotAsRequested(NotAsRequested) {}
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// support for isa<> and dyn_cast.
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static bool classof(const RegAllocPriorityAdvisorAnalysis *R) {
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return R->getAdvisorMode() == AdvisorMode::Default;
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}
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private:
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.addRequired<SlotIndexesWrapperPass>();
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RegAllocPriorityAdvisorAnalysis::getAnalysisUsage(AU);
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}
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std::unique_ptr<RegAllocPriorityAdvisor>
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getAdvisor(const MachineFunction &MF, const RAGreedy &RA) override {
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return std::make_unique<DefaultPriorityAdvisor>(
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MF, RA, &getAnalysis<SlotIndexesWrapperPass>().getSI());
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}
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bool doInitialization(Module &M) override {
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if (NotAsRequested)
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M.getContext().emitError("Requested regalloc priority advisor analysis "
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"could be created. Using default");
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return RegAllocPriorityAdvisorAnalysis::doInitialization(M);
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}
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const bool NotAsRequested;
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};
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class DummyPriorityAdvisorAnalysis final
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: public RegAllocPriorityAdvisorAnalysis {
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public:
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DummyPriorityAdvisorAnalysis()
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: RegAllocPriorityAdvisorAnalysis(AdvisorMode::Dummy) {}
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// support for isa<> and dyn_cast.
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static bool classof(const RegAllocPriorityAdvisorAnalysis *R) {
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return R->getAdvisorMode() == AdvisorMode::Dummy;
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}
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private:
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.addRequired<SlotIndexesWrapperPass>();
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RegAllocPriorityAdvisorAnalysis::getAnalysisUsage(AU);
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}
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std::unique_ptr<RegAllocPriorityAdvisor>
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getAdvisor(const MachineFunction &MF, const RAGreedy &RA) override {
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return std::make_unique<DummyPriorityAdvisor>(
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MF, RA, &getAnalysis<SlotIndexesWrapperPass>().getSI());
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}
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};
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} // namespace
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template <> Pass *llvm::callDefaultCtor<RegAllocPriorityAdvisorAnalysis>() {
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Pass *Ret = nullptr;
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switch (Mode) {
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case RegAllocPriorityAdvisorAnalysis::AdvisorMode::Default:
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Ret = new DefaultPriorityAdvisorAnalysis(/*NotAsRequested*/ false);
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break;
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case RegAllocPriorityAdvisorAnalysis::AdvisorMode::Dummy:
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Ret = new DummyPriorityAdvisorAnalysis();
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break;
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case RegAllocPriorityAdvisorAnalysis::AdvisorMode::Development:
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#if defined(LLVM_HAVE_TFLITE)
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Ret = createDevelopmentModePriorityAdvisor();
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#endif
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break;
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case RegAllocPriorityAdvisorAnalysis::AdvisorMode::Release:
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Ret = createReleaseModePriorityAdvisor();
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break;
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}
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if (Ret)
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return Ret;
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return new DefaultPriorityAdvisorAnalysis(/*NotAsRequested*/ true);
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}
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StringRef RegAllocPriorityAdvisorAnalysis::getPassName() const {
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switch (getAdvisorMode()) {
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case AdvisorMode::Default:
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return "Default Regalloc Priority Advisor";
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case AdvisorMode::Release:
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return "Release mode Regalloc Priority Advisor";
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case AdvisorMode::Development:
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return "Development mode Regalloc Priority Advisor";
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case AdvisorMode::Dummy:
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return "Dummy Regalloc Priority Advisor";
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}
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llvm_unreachable("Unknown advisor kind");
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}
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RegAllocPriorityAdvisor::RegAllocPriorityAdvisor(const MachineFunction &MF,
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const RAGreedy &RA,
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SlotIndexes *const Indexes)
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: RA(RA), LIS(RA.getLiveIntervals()), VRM(RA.getVirtRegMap()),
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MRI(&VRM->getRegInfo()), TRI(MF.getSubtarget().getRegisterInfo()),
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RegClassInfo(RA.getRegClassInfo()), Indexes(Indexes),
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RegClassPriorityTrumpsGlobalness(
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RA.getRegClassPriorityTrumpsGlobalness()),
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ReverseLocalAssignment(RA.getReverseLocalAssignment()) {}
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