82912fd620
This commit bulk-updates the libclc license headers to the current Apache-2.0 WITH LLVM-exception license in situations where they were previously attributed to AMD - and occasionally under an additional single individual contributor - under an MIT license. AMD signed the LLVM relicensing agreement and so agreed for their past contributions under the new LLVM license. The LLVM project also has had a long-standing, unwritten, policy of not adding copyright notices to source code. This policy was recently written up [1]. This commit therefore also removes these copyright notices at the same time. Note that there are outstanding copyright notices attributed to others - and many files missing copyright headers - which will be dealt with in future work. [1] https://llvm.org/docs/DeveloperPolicy.html#embedded-copyright-or-contributed-by-statements
83 lines
2.9 KiB
C++
83 lines
2.9 KiB
C++
//===----------------------------------------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#if __CLC_FPSIZE == 32
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#ifdef __CLC_SCALAR
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_CLC_OVERLOAD _CLC_DEF __CLC_GENTYPE fdim(__CLC_GENTYPE x, __CLC_GENTYPE y) {
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if (__builtin_isnan(x) || __builtin_isnan(y))
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return as_float(QNANBITPATT_SP32);
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return fmax(x - y, 0.0f);
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}
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#define __CLC_FDIM_VEC(width) \
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_CLC_OVERLOAD _CLC_DEF float##width fdim(float##width x, float##width y) { \
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/* Determine if x or y is NaN. */ \
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/* Vector true is -1, i.e. all-bits-set, and NaN==NaN is false. */ \
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/* If either is NaN, then ~((x==x) & (y==y)) will be 0 (e.g. ~(-1)), as will n. */ \
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int##width n = ~((x == x) & (y == y)) & QNANBITPATT_SP32; \
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/* Calculate x-y if x>y, otherwise positive 0, again taking */ \
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/* advantage of vector true being all-bits-set. */ \
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int##width r = (x > y) & as_int##width(x - y); \
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return as_float##width(n | r); \
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}
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__CLC_FDIM_VEC(2)
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__CLC_FDIM_VEC(3)
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__CLC_FDIM_VEC(4)
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__CLC_FDIM_VEC(8)
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__CLC_FDIM_VEC(16)
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#undef __CLC_FDIM_VEC
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#endif
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#endif
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#if __CLC_FPSIZE == 64
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#ifdef __CLC_SCALAR
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_CLC_OVERLOAD _CLC_DEF __CLC_GENTYPE fdim(__CLC_GENTYPE x, private __CLC_GENTYPE y) {
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long n = -(isnan(x) | isnan(y)) & QNANBITPATT_DP64;
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long r = -(x > y) & as_long(x - y);
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return as_double(n | r);
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}
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#define __CLC_FDIM_VEC(width) \
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_CLC_OVERLOAD _CLC_DEF double##width fdim(double##width x, double##width y) { \
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/* See comment in float implementation for explanation. */ \
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long##width n = ~((x == x) & (y == y)) & QNANBITPATT_DP64; \
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long##width r = (x > y) & as_long##width(x - y); \
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return as_double##width(n | r); \
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}
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__CLC_FDIM_VEC(2)
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__CLC_FDIM_VEC(3)
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__CLC_FDIM_VEC(4)
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__CLC_FDIM_VEC(8)
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__CLC_FDIM_VEC(16)
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#undef __CLC_FDIM_VEC
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#endif
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#endif
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#if __CLC_FPSIZE == 16
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#ifdef __CLC_SCALAR
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#define QNANBITPATT_FP16 ((short)0x7e00)
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_CLC_OVERLOAD _CLC_DEF __CLC_GENTYPE fdim(__CLC_GENTYPE x,
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private __CLC_GENTYPE y) {
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short n = -(isnan(x) | isnan(y)) & QNANBITPATT_FP16;
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short r = -(x > y) & as_short(x - y);
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return as_half((short)(n | r));
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}
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#define __CLC_FDIM_VEC(width) \
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_CLC_OVERLOAD _CLC_DEF half##width fdim(half##width x, half##width y) { \
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/* See comment in float implementation for explanation. */ \
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short##width n = ~((x == x) & (y == y)) & QNANBITPATT_FP16; \
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short##width r = (x > y) & as_short##width(x - y); \
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return as_half##width(n | r); \
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}
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__CLC_FDIM_VEC(2)
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__CLC_FDIM_VEC(3)
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__CLC_FDIM_VEC(4)
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__CLC_FDIM_VEC(8)
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__CLC_FDIM_VEC(16)
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#undef __CLC_FDIM_VEC
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#endif
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#endif
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