The `dx.dot2`, `dot3`, and `dot4` intrinsics exist purely to lower `dx.fdot`, and they map exactly to the DXIL ops of the same name. Using vectors for their arguments adds unnecessary complexity and causes us to have vector operations that are not trivial to lower post-scalarizer. Similarly, the `dx.dot2add` intrinsic is overly generic for something that only needs to lower to a single `dot2AddHalf` DXIL op. Update its signature to match the operation it lowers to. Fixes #134569.
1125 lines
40 KiB
TableGen
1125 lines
40 KiB
TableGen
//- DXIL.td - Describe DXIL operation -------------------------*- tablegen -*-//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This is a target description file for DXIL operations.
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///
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//===----------------------------------------------------------------------===//
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include "llvm/IR/Intrinsics.td"
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// Abstract class to represent major and minor version values
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class Version<int major, int minor> {
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int Major = major;
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int Minor = minor;
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}
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// Valid DXIL Version records
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foreach i = 0...8 in {
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def DXIL1_ #i : Version<1, i>;
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}
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class DXILOpParamType {
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int isOverload = 0;
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}
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let isOverload = 1 in {
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def OverloadTy : DXILOpParamType;
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}
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def VoidTy : DXILOpParamType;
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def Int1Ty : DXILOpParamType;
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def Int8Ty : DXILOpParamType;
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def Int16Ty : DXILOpParamType;
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def Int32Ty : DXILOpParamType;
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def Int64Ty : DXILOpParamType;
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def HalfTy : DXILOpParamType;
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def FloatTy : DXILOpParamType;
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def DoubleTy : DXILOpParamType;
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def ResRetHalfTy : DXILOpParamType;
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def ResRetFloatTy : DXILOpParamType;
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def ResRetDoubleTy : DXILOpParamType;
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def ResRetInt16Ty : DXILOpParamType;
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def ResRetInt32Ty : DXILOpParamType;
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def ResRetInt64Ty : DXILOpParamType;
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def CBufRetHalfTy : DXILOpParamType;
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def CBufRetFloatTy : DXILOpParamType;
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def CBufRetDoubleTy : DXILOpParamType;
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def CBufRetInt16Ty : DXILOpParamType;
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def CBufRetInt32Ty : DXILOpParamType;
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def CBufRetInt64Ty : DXILOpParamType;
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def HandleTy : DXILOpParamType;
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def ResBindTy : DXILOpParamType;
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def ResPropsTy : DXILOpParamType;
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def SplitDoubleTy : DXILOpParamType;
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def BinaryWithCarryTy : DXILOpParamType;
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class DXILOpClass;
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defset list<DXILOpClass> OpClasses = {
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def acceptHitAndEndSearch : DXILOpClass;
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def allocateNodeOutputRecords : DXILOpClass;
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def allocateRayQuery : DXILOpClass;
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def annotateHandle : DXILOpClass;
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def annotateNodeHandle : DXILOpClass;
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def annotateNodeRecordHandle : DXILOpClass;
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def atomicBinOp : DXILOpClass;
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def atomicCompareExchange : DXILOpClass;
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def attributeAtVertex : DXILOpClass;
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def barrier : DXILOpClass;
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def barrierByMemoryHandle : DXILOpClass;
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def barrierByMemoryType : DXILOpClass;
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def barrierByNodeRecordHandle : DXILOpClass;
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def binary : DXILOpClass;
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def binaryWithCarryOrBorrow : DXILOpClass;
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def binaryWithTwoOuts : DXILOpClass;
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def bitcastF16toI16 : DXILOpClass;
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def bitcastF32toI32 : DXILOpClass;
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def bitcastF64toI64 : DXILOpClass;
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def bitcastI16toF16 : DXILOpClass;
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def bitcastI32toF32 : DXILOpClass;
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def bitcastI64toF64 : DXILOpClass;
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def bufferLoad : DXILOpClass;
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def bufferStore : DXILOpClass;
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def bufferUpdateCounter : DXILOpClass;
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def calculateLOD : DXILOpClass;
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def callShader : DXILOpClass;
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def cbufferLoad : DXILOpClass;
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def cbufferLoadLegacy : DXILOpClass;
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def checkAccessFullyMapped : DXILOpClass;
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def coverage : DXILOpClass;
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def createHandle : DXILOpClass;
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def createHandleForLib : DXILOpClass;
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def createHandleFromBinding : DXILOpClass;
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def createHandleFromHeap : DXILOpClass;
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def createNodeInputRecordHandle : DXILOpClass;
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def createNodeOutputHandle : DXILOpClass;
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def cutStream : DXILOpClass;
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def cycleCounterLegacy : DXILOpClass;
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def discard : DXILOpClass;
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def dispatchMesh : DXILOpClass;
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def dispatchRaysDimensions : DXILOpClass;
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def dispatchRaysIndex : DXILOpClass;
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def domainLocation : DXILOpClass;
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def dot2 : DXILOpClass;
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def dot2AddHalf : DXILOpClass;
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def dot3 : DXILOpClass;
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def dot4 : DXILOpClass;
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def dot4AddPacked : DXILOpClass;
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def emitIndices : DXILOpClass;
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def emitStream : DXILOpClass;
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def emitThenCutStream : DXILOpClass;
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def evalCentroid : DXILOpClass;
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def evalSampleIndex : DXILOpClass;
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def evalSnapped : DXILOpClass;
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def finishedCrossGroupSharing : DXILOpClass;
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def flattenedThreadIdInGroup : DXILOpClass;
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def geometryIndex : DXILOpClass;
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def getDimensions : DXILOpClass;
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def getInputRecordCount : DXILOpClass;
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def getMeshPayload : DXILOpClass;
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def getNodeRecordPtr : DXILOpClass;
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def getRemainingRecursionLevels : DXILOpClass;
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def groupId : DXILOpClass;
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def gsInstanceID : DXILOpClass;
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def hitKind : DXILOpClass;
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def ignoreHit : DXILOpClass;
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def incrementOutputCount : DXILOpClass;
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def indexNodeHandle : DXILOpClass;
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def innerCoverage : DXILOpClass;
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def instanceID : DXILOpClass;
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def instanceIndex : DXILOpClass;
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def isHelperLane : DXILOpClass;
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def isSpecialFloat : DXILOpClass;
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def legacyDoubleToFloat : DXILOpClass;
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def legacyDoubleToSInt32 : DXILOpClass;
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def legacyDoubleToUInt32 : DXILOpClass;
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def legacyF16ToF32 : DXILOpClass;
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def legacyF32ToF16 : DXILOpClass;
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def loadInput : DXILOpClass;
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def loadOutputControlPoint : DXILOpClass;
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def loadPatchConstant : DXILOpClass;
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def makeDouble : DXILOpClass;
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def minPrecXRegLoad : DXILOpClass;
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def minPrecXRegStore : DXILOpClass;
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def nodeOutputIsValid : DXILOpClass;
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def objectRayDirection : DXILOpClass;
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def objectRayOrigin : DXILOpClass;
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def objectToWorld : DXILOpClass;
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def outputComplete : DXILOpClass;
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def outputControlPointID : DXILOpClass;
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def pack4x8 : DXILOpClass;
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def primitiveID : DXILOpClass;
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def primitiveIndex : DXILOpClass;
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def quadOp : DXILOpClass;
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def quadReadLaneAt : DXILOpClass;
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def quadVote : DXILOpClass;
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def quaternary : DXILOpClass;
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def rawBufferLoad : DXILOpClass;
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def rawBufferStore : DXILOpClass;
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def rayFlags : DXILOpClass;
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def rayQuery_Abort : DXILOpClass;
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def rayQuery_CommitNonOpaqueTriangleHit : DXILOpClass;
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def rayQuery_CommitProceduralPrimitiveHit : DXILOpClass;
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def rayQuery_Proceed : DXILOpClass;
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def rayQuery_StateMatrix : DXILOpClass;
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def rayQuery_StateScalar : DXILOpClass;
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def rayQuery_StateVector : DXILOpClass;
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def rayQuery_TraceRayInline : DXILOpClass;
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def rayTCurrent : DXILOpClass;
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def rayTMin : DXILOpClass;
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def renderTargetGetSampleCount : DXILOpClass;
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def renderTargetGetSamplePosition : DXILOpClass;
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def reportHit : DXILOpClass;
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def sample : DXILOpClass;
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def sampleBias : DXILOpClass;
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def sampleCmp : DXILOpClass;
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def sampleCmpBias : DXILOpClass;
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def sampleCmpGrad : DXILOpClass;
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def sampleCmpLevel : DXILOpClass;
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def sampleCmpLevelZero : DXILOpClass;
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def sampleGrad : DXILOpClass;
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def sampleIndex : DXILOpClass;
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def sampleLevel : DXILOpClass;
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def setMeshOutputCounts : DXILOpClass;
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def splitDouble : DXILOpClass;
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def startInstanceLocation : DXILOpClass;
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def startVertexLocation : DXILOpClass;
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def storeOutput : DXILOpClass;
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def storePatchConstant : DXILOpClass;
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def storePrimitiveOutput : DXILOpClass;
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def storeVertexOutput : DXILOpClass;
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def tempRegLoad : DXILOpClass;
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def tempRegStore : DXILOpClass;
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def tertiary : DXILOpClass;
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def texture2DMSGetSamplePosition : DXILOpClass;
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def textureGather : DXILOpClass;
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def textureGatherCmp : DXILOpClass;
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def textureGatherRaw : DXILOpClass;
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def textureLoad : DXILOpClass;
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def textureStore : DXILOpClass;
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def textureStoreSample : DXILOpClass;
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def threadId : DXILOpClass;
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def threadIdInGroup : DXILOpClass;
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def traceRay : DXILOpClass;
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def unary : DXILOpClass;
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def unaryBits : DXILOpClass;
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def unpack4x8 : DXILOpClass;
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def viewID : DXILOpClass;
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def waveActiveAllEqual : DXILOpClass;
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def waveActiveBallot : DXILOpClass;
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def waveActiveBit : DXILOpClass;
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def waveActiveOp : DXILOpClass;
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def waveAllOp : DXILOpClass;
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def waveAllTrue : DXILOpClass;
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def waveAnyTrue : DXILOpClass;
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def waveGetLaneCount : DXILOpClass;
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def waveGetLaneIndex : DXILOpClass;
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def waveIsFirstLane : DXILOpClass;
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def waveMatch : DXILOpClass;
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def waveMatrix_Accumulate : DXILOpClass;
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def waveMatrix_Annotate : DXILOpClass;
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def waveMatrix_Depth : DXILOpClass;
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def waveMatrix_Fill : DXILOpClass;
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def waveMatrix_LoadGroupShared : DXILOpClass;
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def waveMatrix_LoadRawBuf : DXILOpClass;
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def waveMatrix_Multiply : DXILOpClass;
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def waveMatrix_ScalarOp : DXILOpClass;
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def waveMatrix_StoreGroupShared : DXILOpClass;
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def waveMatrix_StoreRawBuf : DXILOpClass;
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def waveMultiPrefixBitCount : DXILOpClass;
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def waveMultiPrefixOp : DXILOpClass;
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def wavePrefixOp : DXILOpClass;
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def waveReadLaneAt : DXILOpClass;
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def waveReadLaneFirst : DXILOpClass;
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def worldRayDirection : DXILOpClass;
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def worldRayOrigin : DXILOpClass;
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def worldToObject : DXILOpClass;
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def writeSamplerFeedback : DXILOpClass;
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def writeSamplerFeedbackBias : DXILOpClass;
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def writeSamplerFeedbackGrad : DXILOpClass;
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def writeSamplerFeedbackLevel : DXILOpClass;
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// This is a sentinel definition. Hence placed at the end here and
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// not as part of the above alphabetically sorted valid definitions.
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// It is never used to construct the name of DXIL Op call name.
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// Additionally it is capitalized unlike all the others.
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def UnknownOpClass : DXILOpClass;
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}
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class DXILShaderStage;
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def compute : DXILShaderStage;
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def domain : DXILShaderStage;
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def hull : DXILShaderStage;
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def pixel : DXILShaderStage;
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def vertex : DXILShaderStage;
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def geometry : DXILShaderStage;
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def library : DXILShaderStage;
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def amplification : DXILShaderStage;
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def mesh : DXILShaderStage;
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def node : DXILShaderStage;
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def raygeneration : DXILShaderStage;
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def intersection : DXILShaderStage;
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def anyhit : DXILShaderStage;
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def closesthit : DXILShaderStage;
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def callable : DXILShaderStage;
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def miss : DXILShaderStage;
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// Pseudo-stages
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// Denote DXIL Op to be supported in all stages
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def all_stages : DXILShaderStage;
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// Denote support for DXIL Op to have been removed
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def removed : DXILShaderStage;
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// DXIL Op attributes
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// A function attribute denotes that there is a corresponding LLVM function
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// attribute that will be set when building the DXIL op. The mapping is defined
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// by setDXILAttributes in DXILOpBuilder.cpp
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class DXILAttribute;
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def ReadNone : DXILAttribute;
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def ReadOnly : DXILAttribute;
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def NoDuplicate : DXILAttribute;
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def NoReturn : DXILAttribute;
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class Overloads<Version ver, list<DXILOpParamType> ols> {
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Version dxil_version = ver;
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list<DXILOpParamType> overload_types = ols;
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}
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class Stages<Version ver, list<DXILShaderStage> st> {
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Version dxil_version = ver;
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list<DXILShaderStage> shader_stages = st;
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}
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class Attributes<Version ver = DXIL1_0, list<DXILAttribute> attrs> {
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Version dxil_version = ver;
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list<DXILAttribute> fn_attrs = attrs;
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}
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defvar BarrierMode_DeviceMemoryBarrier = 2;
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defvar BarrierMode_DeviceMemoryBarrierWithGroupSync = 3;
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defvar BarrierMode_GroupMemoryBarrier = 8;
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defvar BarrierMode_GroupMemoryBarrierWithGroupSync = 9;
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defvar BarrierMode_AllMemoryBarrier = 10;
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defvar BarrierMode_AllMemoryBarrierWithGroupSync = 11;
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defvar WaveOpKind_Sum = 0;
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defvar WaveOpKind_Product = 1;
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defvar WaveOpKind_Min = 2;
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defvar WaveOpKind_Max = 3;
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defvar SignedOpKind_Signed = 0;
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defvar SignedOpKind_Unsigned = 1;
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// Intrinsic arg selection
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class IntrinArgSelectType;
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def IntrinArgSelect_Index : IntrinArgSelectType;
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def IntrinArgSelect_I8 : IntrinArgSelectType;
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def IntrinArgSelect_I32 : IntrinArgSelectType;
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class IntrinArgSelect<IntrinArgSelectType type_, int value_> {
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IntrinArgSelectType type = type_;
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int value = value_;
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}
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class IntrinArgIndex<int index> : IntrinArgSelect<IntrinArgSelect_Index, index>;
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class IntrinArgI8<int value> : IntrinArgSelect<IntrinArgSelect_I8, value>;
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class IntrinArgI32<int value> : IntrinArgSelect<IntrinArgSelect_I32, value>;
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// Select which intrinsic to lower from for a DXILOp.
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// If the intrinsic is the only argument given to IntrinSelect, then the
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// arguments of the intrinsic will be copied in the same order. Example:
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// let intrinsics = [
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// IntrinSelect<int_dx_my_intrinsic>,
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// IntrinSelect<int_dx_my_intrinsic2>,
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// ]
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//=========================================================================================
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// Using IntrinArgIndex<>, arguments of the intrinsic can be copied to the DXIL
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// OP in specific order:
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// let intrinsics = [
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// IntrinSelect<int_dx_my_intrinsic,
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// [IntrinArgIndex<2>, IntrinArgIndex<1>, IntrinArgIndex<0>> ]
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// >,
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// ]
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//=========================================================================================
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// Using IntrinArgI8<> and IntrinArgI32<>, integer constants can be added
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// directly to the dxil op. This can be used in conjunction with
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// IntrinArgIndex:
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// let intrinsics = [
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// IntrinSelect<int_dx_wave_active_usum,
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// [ IntrinArgIndex<0>, IntrinArgI8<0>, IntrinArgI8<1> ]
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// >,
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// IntrinSelect<int_dx_wave_reduce_sum,
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// [ IntrinArgIndex<0>, IntrinArgI8<0>, IntrinArgI8<0> ]
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// >,
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// ]
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//
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class IntrinSelect<Intrinsic intrinsic_,
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list<IntrinArgSelect> arg_selects_ = []> {
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Intrinsic intrinsic = intrinsic_;
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list<IntrinArgSelect> arg_selects = arg_selects_;
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}
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// Abstraction DXIL Operation
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class DXILOp<int opcode, DXILOpClass opclass> {
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// A short description of the operation
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string Doc = "";
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// Opcode of DXIL Operation
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int OpCode = opcode;
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// Class of DXIL Operation.
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DXILOpClass OpClass = opclass;
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// LLVM Intrinsics DXIL Operation maps from
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list<IntrinSelect> intrinsics = [];
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// Result type of the op
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DXILOpParamType result;
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// List of argument types of the op. Default to 0 arguments.
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list<DXILOpParamType> arguments = [];
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// List of valid overload types predicated by DXIL version
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list<Overloads> overloads = [];
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// List of valid shader stages predicated by DXIL version
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list<Stages> stages;
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// Versioned attributes of operation
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list<Attributes> attributes = [];
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}
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// Concrete definitions of DXIL Operations
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//
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// This are sorted by ascending value of the DXIL Opcodes
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def Abs : DXILOp<6, unary> {
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let Doc = "Returns the absolute value of the input.";
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let intrinsics = [IntrinSelect<int_fabs>];
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let arguments = [OverloadTy];
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let result = OverloadTy;
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let overloads = [Overloads<DXIL1_0, [HalfTy, FloatTy, DoubleTy]>];
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let stages = [Stages<DXIL1_0, [all_stages]>];
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let attributes = [Attributes<DXIL1_0, [ReadNone]>];
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}
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def Saturate : DXILOp<7, unary> {
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let Doc = "Clamps a single or double precision floating point value to "
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"[0.0f...1.0f].";
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let intrinsics = [IntrinSelect<int_dx_saturate>];
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let arguments = [OverloadTy];
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let result = OverloadTy;
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let overloads = [Overloads<DXIL1_0, [HalfTy, FloatTy, DoubleTy]>];
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let stages = [Stages<DXIL1_0, [all_stages]>];
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let attributes = [Attributes<DXIL1_0, [ReadNone]>];
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}
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def IsInf : DXILOp<9, isSpecialFloat> {
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let Doc = "Determines if the specified value is infinite.";
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let intrinsics = [IntrinSelect<int_dx_isinf>];
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let arguments = [OverloadTy];
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let result = Int1Ty;
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let overloads = [Overloads<DXIL1_0, [HalfTy, FloatTy]>];
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let stages = [Stages<DXIL1_0, [all_stages]>];
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let attributes = [Attributes<DXIL1_0, [ReadNone]>];
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}
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def Cos : DXILOp<12, unary> {
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let Doc = "Returns cosine(theta) for theta in radians.";
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let intrinsics = [IntrinSelect<int_cos>];
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let arguments = [OverloadTy];
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let result = OverloadTy;
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let overloads = [Overloads<DXIL1_0, [HalfTy, FloatTy]>];
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let stages = [Stages<DXIL1_0, [all_stages]>];
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let attributes = [Attributes<DXIL1_0, [ReadNone]>];
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}
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def Sin : DXILOp<13, unary> {
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let Doc = "Returns sine(theta) for theta in radians.";
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let intrinsics = [IntrinSelect<int_sin>];
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let arguments = [OverloadTy];
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let result = OverloadTy;
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let overloads = [Overloads<DXIL1_0, [HalfTy, FloatTy]>];
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let stages = [Stages<DXIL1_0, [all_stages]>];
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let attributes = [Attributes<DXIL1_0, [ReadNone]>];
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}
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def Tan : DXILOp<14, unary> {
|
|
let Doc = "Returns tangent(theta) for theta in radians.";
|
|
let intrinsics = [IntrinSelect<int_tan>];
|
|
let arguments = [OverloadTy];
|
|
let result = OverloadTy;
|
|
let overloads = [Overloads<DXIL1_0, [HalfTy, FloatTy]>];
|
|
let stages = [Stages<DXIL1_0, [all_stages]>];
|
|
let attributes = [Attributes<DXIL1_0, [ReadNone]>];
|
|
}
|
|
|
|
def ACos : DXILOp<15, unary> {
|
|
let Doc = "Returns the arccosine of the specified value.";
|
|
let intrinsics = [IntrinSelect<int_acos>];
|
|
let arguments = [OverloadTy];
|
|
let result = OverloadTy;
|
|
let overloads = [Overloads<DXIL1_0, [HalfTy, FloatTy]>];
|
|
let stages = [Stages<DXIL1_0, [all_stages]>];
|
|
let attributes = [Attributes<DXIL1_0, [ReadNone]>];
|
|
}
|
|
|
|
def ASin : DXILOp<16, unary> {
|
|
let Doc = "Returns the arcsine of the specified value.";
|
|
let intrinsics = [IntrinSelect<int_asin>];
|
|
let arguments = [OverloadTy];
|
|
let result = OverloadTy;
|
|
let overloads = [Overloads<DXIL1_0, [HalfTy, FloatTy]>];
|
|
let stages = [Stages<DXIL1_0, [all_stages]>];
|
|
let attributes = [Attributes<DXIL1_0, [ReadNone]>];
|
|
}
|
|
|
|
def ATan : DXILOp<17, unary> {
|
|
let Doc = "Returns the arctangent of the specified value.";
|
|
let intrinsics = [IntrinSelect<int_atan>];
|
|
let arguments = [OverloadTy];
|
|
let result = OverloadTy;
|
|
let overloads = [Overloads<DXIL1_0, [HalfTy, FloatTy]>];
|
|
let stages = [Stages<DXIL1_0, [all_stages]>];
|
|
let attributes = [Attributes<DXIL1_0, [ReadNone]>];
|
|
}
|
|
|
|
def HCos : DXILOp<18, unary> {
|
|
let Doc = "Returns the hyperbolic cosine of the specified value.";
|
|
let intrinsics = [IntrinSelect<int_cosh>];
|
|
let arguments = [OverloadTy];
|
|
let result = OverloadTy;
|
|
let overloads = [Overloads<DXIL1_0, [HalfTy, FloatTy]>];
|
|
let stages = [Stages<DXIL1_0, [all_stages]>];
|
|
let attributes = [Attributes<DXIL1_0, [ReadNone]>];
|
|
}
|
|
|
|
def HSin : DXILOp<19, unary> {
|
|
let Doc = "Returns the hyperbolic sine of the specified value.";
|
|
let intrinsics = [IntrinSelect<int_sinh>];
|
|
let arguments = [OverloadTy];
|
|
let result = OverloadTy;
|
|
let overloads = [Overloads<DXIL1_0, [HalfTy, FloatTy]>];
|
|
let stages = [Stages<DXIL1_0, [all_stages]>];
|
|
let attributes = [Attributes<DXIL1_0, [ReadNone]>];
|
|
}
|
|
|
|
def HTan : DXILOp<20, unary> {
|
|
let Doc = "Returns the hyperbolic tan of the specified value.";
|
|
let intrinsics = [IntrinSelect<int_tanh>];
|
|
let arguments = [OverloadTy];
|
|
let result = OverloadTy;
|
|
let overloads = [Overloads<DXIL1_0, [HalfTy, FloatTy]>];
|
|
let stages = [Stages<DXIL1_0, [all_stages]>];
|
|
let attributes = [Attributes<DXIL1_0, [ReadNone]>];
|
|
}
|
|
|
|
def Exp2 : DXILOp<21, unary> {
|
|
let Doc = "Returns the base 2 exponential, or 2**x, of the specified value. "
|
|
"exp2(x) = 2**x.";
|
|
let intrinsics = [IntrinSelect<int_exp2>];
|
|
let arguments = [OverloadTy];
|
|
let result = OverloadTy;
|
|
let overloads = [Overloads<DXIL1_0, [HalfTy, FloatTy]>];
|
|
let stages = [Stages<DXIL1_0, [all_stages]>];
|
|
let attributes = [Attributes<DXIL1_0, [ReadNone]>];
|
|
}
|
|
|
|
def Frac : DXILOp<22, unary> {
|
|
let Doc = "Returns a fraction from 0 to 1 that represents the decimal part "
|
|
"of the input.";
|
|
let intrinsics = [IntrinSelect<int_dx_frac>];
|
|
let arguments = [OverloadTy];
|
|
let result = OverloadTy;
|
|
let overloads = [Overloads<DXIL1_0, [HalfTy, FloatTy]>];
|
|
let stages = [Stages<DXIL1_0, [all_stages]>];
|
|
let attributes = [Attributes<DXIL1_0, [ReadNone]>];
|
|
}
|
|
|
|
def Log2 : DXILOp<23, unary> {
|
|
let Doc = "Returns the base-2 logarithm of the specified value.";
|
|
let intrinsics = [IntrinSelect<int_log2>];
|
|
let arguments = [OverloadTy];
|
|
let result = OverloadTy;
|
|
let overloads = [Overloads<DXIL1_0, [HalfTy, FloatTy]>];
|
|
let stages = [Stages<DXIL1_0, [all_stages]>];
|
|
let attributes = [Attributes<DXIL1_0, [ReadNone]>];
|
|
}
|
|
|
|
def Sqrt : DXILOp<24, unary> {
|
|
let Doc = "Returns the square root of the specified floating-point value, "
|
|
"per component.";
|
|
let intrinsics = [IntrinSelect<int_sqrt>];
|
|
let arguments = [OverloadTy];
|
|
let result = OverloadTy;
|
|
let overloads = [Overloads<DXIL1_0, [HalfTy, FloatTy]>];
|
|
let stages = [Stages<DXIL1_0, [all_stages]>];
|
|
let attributes = [Attributes<DXIL1_0, [ReadNone]>];
|
|
}
|
|
|
|
def RSqrt : DXILOp<25, unary> {
|
|
let Doc = "Returns the reciprocal of the square root of the specified value. "
|
|
"rsqrt(x) = 1 / sqrt(x).";
|
|
let intrinsics = [IntrinSelect<int_dx_rsqrt>];
|
|
let arguments = [OverloadTy];
|
|
let result = OverloadTy;
|
|
let overloads = [Overloads<DXIL1_0, [HalfTy, FloatTy]>];
|
|
let stages = [Stages<DXIL1_0, [all_stages]>];
|
|
let attributes = [Attributes<DXIL1_0, [ReadNone]>];
|
|
}
|
|
|
|
def Round : DXILOp<26, unary> {
|
|
let Doc = "Returns the input rounded to the nearest integer within a "
|
|
"floating-point type.";
|
|
let intrinsics = [IntrinSelect<int_roundeven>];
|
|
let arguments = [OverloadTy];
|
|
let result = OverloadTy;
|
|
let overloads = [Overloads<DXIL1_0, [HalfTy, FloatTy]>];
|
|
let stages = [Stages<DXIL1_0, [all_stages]>];
|
|
let attributes = [Attributes<DXIL1_0, [ReadNone]>];
|
|
}
|
|
|
|
def Floor : DXILOp<27, unary> {
|
|
let Doc =
|
|
"Returns the largest integer that is less than or equal to the input.";
|
|
let intrinsics = [IntrinSelect<int_floor>];
|
|
let arguments = [OverloadTy];
|
|
let result = OverloadTy;
|
|
let overloads = [Overloads<DXIL1_0, [HalfTy, FloatTy]>];
|
|
let stages = [Stages<DXIL1_0, [all_stages]>];
|
|
let attributes = [Attributes<DXIL1_0, [ReadNone]>];
|
|
}
|
|
|
|
def Ceil : DXILOp<28, unary> {
|
|
let Doc = "Returns the smallest integer that is greater than or equal to the "
|
|
"input.";
|
|
let intrinsics = [IntrinSelect<int_ceil>];
|
|
let arguments = [OverloadTy];
|
|
let result = OverloadTy;
|
|
let overloads = [Overloads<DXIL1_0, [HalfTy, FloatTy]>];
|
|
let stages = [Stages<DXIL1_0, [all_stages]>];
|
|
let attributes = [Attributes<DXIL1_0, [ReadNone]>];
|
|
}
|
|
|
|
def Trunc : DXILOp<29, unary> {
|
|
let Doc = "Returns the specified value truncated to the integer component.";
|
|
let intrinsics = [IntrinSelect<int_trunc>];
|
|
let arguments = [OverloadTy];
|
|
let result = OverloadTy;
|
|
let overloads = [Overloads<DXIL1_0, [HalfTy, FloatTy]>];
|
|
let stages = [Stages<DXIL1_0, [all_stages]>];
|
|
let attributes = [Attributes<DXIL1_0, [ReadNone]>];
|
|
}
|
|
|
|
def Rbits : DXILOp<30, unary> {
|
|
let Doc = "Returns the specified value with its bits reversed.";
|
|
let intrinsics = [IntrinSelect<int_bitreverse>];
|
|
let arguments = [OverloadTy];
|
|
let result = OverloadTy;
|
|
let overloads = [Overloads<DXIL1_0, [Int16Ty, Int32Ty, Int64Ty]>];
|
|
let stages = [Stages<DXIL1_0, [all_stages]>];
|
|
let attributes = [Attributes<DXIL1_0, [ReadNone]>];
|
|
}
|
|
|
|
def CountBits : DXILOp<31, unaryBits> {
|
|
let Doc = "Returns the number of 1 bits in the specified value.";
|
|
let arguments = [OverloadTy];
|
|
let result = Int32Ty;
|
|
let overloads = [Overloads<DXIL1_0, [Int16Ty, Int32Ty, Int64Ty]>];
|
|
let stages = [Stages<DXIL1_0, [all_stages]>];
|
|
let attributes = [Attributes<DXIL1_0, [ReadNone]>];
|
|
}
|
|
|
|
def FirstbitLo : DXILOp<32, unaryBits> {
|
|
let Doc = "Returns the location of the first set bit starting from "
|
|
"the lowest order bit and working upward.";
|
|
let intrinsics = [IntrinSelect<int_dx_firstbitlow>];
|
|
let arguments = [OverloadTy];
|
|
let result = Int32Ty;
|
|
let overloads = [Overloads<DXIL1_0, [Int16Ty, Int32Ty, Int64Ty]>];
|
|
let stages = [Stages<DXIL1_0, [all_stages]>];
|
|
let attributes = [Attributes<DXIL1_0, [ReadNone]>];
|
|
}
|
|
|
|
def FirstbitHi : DXILOp<33, unaryBits> {
|
|
let Doc = "Returns the location of the first set bit starting from "
|
|
"the highest order bit and working downward.";
|
|
let intrinsics = [IntrinSelect<int_dx_firstbituhigh>];
|
|
let arguments = [OverloadTy];
|
|
let result = Int32Ty;
|
|
let overloads = [Overloads<DXIL1_0, [Int16Ty, Int32Ty, Int64Ty]>];
|
|
let stages = [Stages<DXIL1_0, [all_stages]>];
|
|
let attributes = [Attributes<DXIL1_0, [ReadNone]>];
|
|
}
|
|
|
|
def FirstbitSHi : DXILOp<34, unaryBits> {
|
|
let Doc = "Returns the location of the first set bit from "
|
|
"the highest order bit based on the sign.";
|
|
let intrinsics = [IntrinSelect<int_dx_firstbitshigh>];
|
|
let arguments = [OverloadTy];
|
|
let result = Int32Ty;
|
|
let overloads = [Overloads<DXIL1_0, [Int16Ty, Int32Ty, Int64Ty]>];
|
|
let stages = [Stages<DXIL1_0, [all_stages]>];
|
|
let attributes = [Attributes<DXIL1_0, [ReadNone]>];
|
|
}
|
|
|
|
def FMax : DXILOp<35, binary> {
|
|
let Doc = "Float maximum. FMax(a,b) = a > b ? a : b";
|
|
let intrinsics = [IntrinSelect<int_maxnum>];
|
|
let arguments = [OverloadTy, OverloadTy];
|
|
let result = OverloadTy;
|
|
let overloads = [Overloads<DXIL1_0, [HalfTy, FloatTy, DoubleTy]>];
|
|
let stages = [Stages<DXIL1_0, [all_stages]>];
|
|
let attributes = [Attributes<DXIL1_0, [ReadNone]>];
|
|
}
|
|
|
|
def FMin : DXILOp<36, binary> {
|
|
let Doc = "Float minimum. FMin(a,b) = a < b ? a : b";
|
|
let intrinsics = [IntrinSelect<int_minnum>];
|
|
let arguments = [OverloadTy, OverloadTy];
|
|
let result = OverloadTy;
|
|
let overloads = [Overloads<DXIL1_0, [HalfTy, FloatTy, DoubleTy]>];
|
|
let stages = [Stages<DXIL1_0, [all_stages]>];
|
|
let attributes = [Attributes<DXIL1_0, [ReadNone]>];
|
|
}
|
|
|
|
def SMax : DXILOp<37, binary> {
|
|
let Doc = "Signed integer maximum. SMax(a,b) = a > b ? a : b";
|
|
let intrinsics = [IntrinSelect<int_smax>];
|
|
let arguments = [OverloadTy, OverloadTy];
|
|
let result = OverloadTy;
|
|
let overloads = [Overloads<DXIL1_0, [Int16Ty, Int32Ty, Int64Ty]>];
|
|
let stages = [Stages<DXIL1_0, [all_stages]>];
|
|
let attributes = [Attributes<DXIL1_0, [ReadNone]>];
|
|
}
|
|
|
|
def SMin : DXILOp<38, binary> {
|
|
let Doc = "Signed integer minimum. SMin(a,b) = a < b ? a : b";
|
|
let intrinsics = [IntrinSelect<int_smin>];
|
|
let arguments = [OverloadTy, OverloadTy];
|
|
let result = OverloadTy;
|
|
let overloads = [Overloads<DXIL1_0, [Int16Ty, Int32Ty, Int64Ty]>];
|
|
let stages = [Stages<DXIL1_0, [all_stages]>];
|
|
let attributes = [Attributes<DXIL1_0, [ReadNone]>];
|
|
}
|
|
|
|
def UMax : DXILOp<39, binary> {
|
|
let Doc = "Unsigned integer maximum. UMax(a,b) = a > b ? a : b";
|
|
let intrinsics = [IntrinSelect<int_umax>];
|
|
let arguments = [OverloadTy, OverloadTy];
|
|
let result = OverloadTy;
|
|
let overloads = [Overloads<DXIL1_0, [Int16Ty, Int32Ty, Int64Ty]>];
|
|
let stages = [Stages<DXIL1_0, [all_stages]>];
|
|
let attributes = [Attributes<DXIL1_0, [ReadNone]>];
|
|
}
|
|
|
|
def UMin : DXILOp<40, binary> {
|
|
let Doc = "Unsigned integer minimum. UMin(a,b) = a < b ? a : b";
|
|
let intrinsics = [IntrinSelect<int_umin>];
|
|
let arguments = [OverloadTy, OverloadTy];
|
|
let result = OverloadTy;
|
|
let overloads = [Overloads<DXIL1_0, [Int16Ty, Int32Ty, Int64Ty]>];
|
|
let stages = [Stages<DXIL1_0, [all_stages]>];
|
|
let attributes = [Attributes<DXIL1_0, [ReadNone]>];
|
|
}
|
|
|
|
def UAddc : DXILOp<44, binaryWithCarryOrBorrow > {
|
|
let Doc = "unsigned add of 32-bit operand with the carry";
|
|
let intrinsics = [IntrinSelect<int_uadd_with_overflow>];
|
|
let arguments = [OverloadTy, OverloadTy];
|
|
let result = BinaryWithCarryTy;
|
|
let overloads = [Overloads<DXIL1_0, [Int32Ty]>];
|
|
let stages = [Stages<DXIL1_0, [all_stages]>];
|
|
let attributes = [Attributes<DXIL1_0, [ReadNone]>];
|
|
}
|
|
|
|
def FMad : DXILOp<46, tertiary> {
|
|
let Doc = "Floating point arithmetic multiply/add operation. fmad(m,a,b) = m "
|
|
"* a + b.";
|
|
let intrinsics = [IntrinSelect<int_fmuladd>];
|
|
let arguments = [OverloadTy, OverloadTy, OverloadTy];
|
|
let result = OverloadTy;
|
|
let overloads = [Overloads<DXIL1_0, [HalfTy, FloatTy, DoubleTy]>];
|
|
let stages = [Stages<DXIL1_0, [all_stages]>];
|
|
let attributes = [Attributes<DXIL1_0, [ReadNone]>];
|
|
}
|
|
|
|
def IMad : DXILOp<48, tertiary> {
|
|
let Doc = "Signed integer arithmetic multiply/add operation. imad(m,a,b) = m "
|
|
"* a + b.";
|
|
let intrinsics = [IntrinSelect<int_dx_imad>];
|
|
let arguments = [OverloadTy, OverloadTy, OverloadTy];
|
|
let result = OverloadTy;
|
|
let overloads = [Overloads<DXIL1_0, [Int16Ty, Int32Ty, Int64Ty]>];
|
|
let stages = [Stages<DXIL1_0, [all_stages]>];
|
|
let attributes = [Attributes<DXIL1_0, [ReadNone]>];
|
|
}
|
|
|
|
def UMad : DXILOp<49, tertiary> {
|
|
let Doc = "Unsigned integer arithmetic multiply/add operation. umad(m,a, = m "
|
|
"* a + b.";
|
|
let intrinsics = [IntrinSelect<int_dx_umad>];
|
|
let arguments = [OverloadTy, OverloadTy, OverloadTy];
|
|
let result = OverloadTy;
|
|
let overloads = [Overloads<DXIL1_0, [Int16Ty, Int32Ty, Int64Ty]>];
|
|
let stages = [Stages<DXIL1_0, [all_stages]>];
|
|
let attributes = [Attributes<DXIL1_0, [ReadNone]>];
|
|
}
|
|
|
|
def Dot2 : DXILOp<54, dot2> {
|
|
let Doc = "dot product of two float vectors Dot(a,b) = a[0]*b[0] + ... + "
|
|
"a[n]*b[n] where n is 0 to 1 inclusive";
|
|
let intrinsics = [IntrinSelect<int_dx_dot2>];
|
|
let arguments = !listsplat(OverloadTy, 4);
|
|
let result = OverloadTy;
|
|
let overloads = [Overloads<DXIL1_0, [HalfTy, FloatTy]>];
|
|
let stages = [Stages<DXIL1_0, [all_stages]>];
|
|
let attributes = [Attributes<DXIL1_0, [ReadNone]>];
|
|
}
|
|
|
|
def Dot3 : DXILOp<55, dot3> {
|
|
let Doc = "dot product of two float vectors Dot(a,b) = a[0]*b[0] + ... + "
|
|
"a[n]*b[n] where n is 0 to 2 inclusive";
|
|
let intrinsics = [IntrinSelect<int_dx_dot3>];
|
|
let arguments = !listsplat(OverloadTy, 6);
|
|
let result = OverloadTy;
|
|
let overloads = [Overloads<DXIL1_0, [HalfTy, FloatTy]>];
|
|
let stages = [Stages<DXIL1_0, [all_stages]>];
|
|
let attributes = [Attributes<DXIL1_0, [ReadNone]>];
|
|
}
|
|
|
|
def Dot4 : DXILOp<56, dot4> {
|
|
let Doc = "dot product of two float vectors Dot(a,b) = a[0]*b[0] + ... + "
|
|
"a[n]*b[n] where n is 0 to 3 inclusive";
|
|
let intrinsics = [IntrinSelect<int_dx_dot4>];
|
|
let arguments = !listsplat(OverloadTy, 8);
|
|
let result = OverloadTy;
|
|
let overloads = [Overloads<DXIL1_0, [HalfTy, FloatTy]>];
|
|
let stages = [Stages<DXIL1_0, [all_stages]>];
|
|
let attributes = [Attributes<DXIL1_0, [ReadNone]>];
|
|
}
|
|
|
|
def CreateHandle : DXILOp<57, createHandle> {
|
|
let Doc = "creates the handle to a resource";
|
|
// ResourceClass, RangeID, Index, NonUniform
|
|
let arguments = [Int8Ty, Int32Ty, Int32Ty, Int1Ty];
|
|
let result = HandleTy;
|
|
let stages = [Stages<DXIL1_0, [all_stages]>, Stages<DXIL1_6, [removed]>];
|
|
// NOTE: The ReadOnly attribute was set for consistency with DXC. However, it
|
|
// seems like ReadNone may more appropiately describe it. So noted to
|
|
// consider a change in the future
|
|
let attributes = [Attributes<DXIL1_0, [ReadOnly]>];
|
|
}
|
|
|
|
def CBufferLoadLegacy : DXILOp<59, cbufferLoadLegacy> {
|
|
let Doc = "loads a value from a constant buffer resource";
|
|
// Handle, Index
|
|
let arguments = [HandleTy, Int32Ty];
|
|
let result = OverloadTy;
|
|
let overloads = [Overloads<DXIL1_0, [
|
|
CBufRetHalfTy, CBufRetFloatTy, CBufRetDoubleTy, CBufRetInt16Ty,
|
|
CBufRetInt32Ty, CBufRetInt64Ty
|
|
]>];
|
|
let stages = [Stages<DXIL1_0, [all_stages]>];
|
|
let attributes = [Attributes<DXIL1_0, [ReadOnly]>];
|
|
}
|
|
|
|
def BufferLoad : DXILOp<68, bufferLoad> {
|
|
let Doc = "reads from a TypedBuffer";
|
|
// Handle, Coord0, Coord1
|
|
let arguments = [HandleTy, Int32Ty, Int32Ty];
|
|
let result = OverloadTy;
|
|
let overloads =
|
|
[Overloads<DXIL1_0,
|
|
[ResRetHalfTy, ResRetFloatTy, ResRetInt16Ty, ResRetInt32Ty]>];
|
|
let stages = [Stages<DXIL1_0, [all_stages]>];
|
|
let attributes = [Attributes<DXIL1_0, [ReadOnly]>];
|
|
}
|
|
|
|
def BufferStore : DXILOp<69, bufferStore> {
|
|
let Doc = "writes to an RWTypedBuffer";
|
|
// Handle, Coord0, Coord1, Val0, Val1, Val2, Val3, Mask
|
|
let arguments = [
|
|
HandleTy, Int32Ty, Int32Ty, OverloadTy, OverloadTy, OverloadTy, OverloadTy,
|
|
Int8Ty
|
|
];
|
|
let result = VoidTy;
|
|
let overloads = [Overloads<DXIL1_0, [HalfTy, FloatTy, Int16Ty, Int32Ty]>];
|
|
let stages = [Stages<DXIL1_0, [all_stages]>];
|
|
}
|
|
|
|
def UpdateCounter : DXILOp<70, bufferUpdateCounter> {
|
|
let Doc = "increments/decrements a buffer counter";
|
|
let arguments = [HandleTy, Int8Ty];
|
|
let result = Int32Ty;
|
|
let stages = [Stages<DXIL1_0, [all_stages]>];
|
|
}
|
|
|
|
def CheckAccessFullyMapped : DXILOp<71, checkAccessFullyMapped> {
|
|
let Doc = "checks whether a Sample, Gather, or Load operation "
|
|
"accessed mapped tiles in a tiled resource";
|
|
let arguments = [OverloadTy];
|
|
let result = Int1Ty;
|
|
let overloads = [Overloads<DXIL1_0, [Int32Ty]>];
|
|
let stages = [Stages<DXIL1_0, [all_stages]>];
|
|
let attributes = [Attributes<DXIL1_0, [ReadOnly]>];
|
|
}
|
|
|
|
def Barrier : DXILOp<80, barrier> {
|
|
let Doc = "inserts a memory barrier in the shader";
|
|
let intrinsics = [
|
|
IntrinSelect<int_dx_group_memory_barrier_with_group_sync,
|
|
[IntrinArgI32<BarrierMode_GroupMemoryBarrierWithGroupSync>]>,
|
|
];
|
|
|
|
let arguments = [Int32Ty];
|
|
let result = VoidTy;
|
|
let stages = [Stages<DXIL1_0, [compute, library]>];
|
|
let attributes = [Attributes<DXIL1_0, []>];
|
|
}
|
|
|
|
def Discard : DXILOp<82, discard> {
|
|
let Doc = "discard the current pixel";
|
|
let intrinsics = [IntrinSelect<int_dx_discard>];
|
|
let arguments = [Int1Ty];
|
|
let result = VoidTy;
|
|
let stages = [Stages<DXIL1_0, [pixel]>];
|
|
}
|
|
|
|
def ThreadId : DXILOp<93, threadId> {
|
|
let Doc = "Reads the thread ID";
|
|
let intrinsics = [IntrinSelect<int_dx_thread_id>];
|
|
let arguments = [OverloadTy];
|
|
let result = OverloadTy;
|
|
let overloads = [Overloads<DXIL1_0, [Int32Ty]>];
|
|
let stages = [Stages<DXIL1_0, [compute, mesh, amplification, node]>];
|
|
let attributes = [Attributes<DXIL1_0, [ReadNone]>];
|
|
}
|
|
|
|
def GroupId : DXILOp<94, groupId> {
|
|
let Doc = "Reads the group ID (SV_GroupID)";
|
|
let intrinsics = [IntrinSelect<int_dx_group_id>];
|
|
let arguments = [OverloadTy];
|
|
let result = OverloadTy;
|
|
let overloads = [Overloads<DXIL1_0, [Int32Ty]>];
|
|
let stages = [Stages<DXIL1_0, [compute, mesh, amplification, node]>];
|
|
let attributes = [Attributes<DXIL1_0, [ReadNone]>];
|
|
}
|
|
|
|
def ThreadIdInGroup : DXILOp<95, threadIdInGroup> {
|
|
let Doc = "Reads the thread ID within the group (SV_GroupThreadID)";
|
|
let intrinsics = [IntrinSelect<int_dx_thread_id_in_group>];
|
|
let arguments = [OverloadTy];
|
|
let result = OverloadTy;
|
|
let overloads = [Overloads<DXIL1_0, [Int32Ty]>];
|
|
let stages = [Stages<DXIL1_0, [compute, mesh, amplification, node]>];
|
|
let attributes = [Attributes<DXIL1_0, [ReadNone]>];
|
|
}
|
|
|
|
def FlattenedThreadIdInGroup : DXILOp<96, flattenedThreadIdInGroup> {
|
|
let Doc = "Provides a flattened index for a given thread within a given "
|
|
"group (SV_GroupIndex)";
|
|
let intrinsics = [IntrinSelect<int_dx_flattened_thread_id_in_group>];
|
|
let result = OverloadTy;
|
|
let overloads = [Overloads<DXIL1_0, [Int32Ty]>];
|
|
let stages = [Stages<DXIL1_0, [compute, mesh, amplification, node]>];
|
|
let attributes = [Attributes<DXIL1_0, [ReadNone]>];
|
|
}
|
|
|
|
def MakeDouble : DXILOp<101, makeDouble> {
|
|
let Doc = "creates a double value";
|
|
let intrinsics = [IntrinSelect<int_dx_asdouble>];
|
|
let arguments = [Int32Ty, Int32Ty];
|
|
let result = DoubleTy;
|
|
let stages = [Stages<DXIL1_0, [all_stages]>];
|
|
let attributes = [Attributes<DXIL1_0, [ReadNone]>];
|
|
}
|
|
|
|
def SplitDouble : DXILOp<102, splitDouble> {
|
|
let Doc = "Splits a double into 2 uints";
|
|
let intrinsics = [IntrinSelect<int_dx_splitdouble>];
|
|
let arguments = [OverloadTy];
|
|
let result = SplitDoubleTy;
|
|
let overloads = [Overloads<DXIL1_0, [DoubleTy]>];
|
|
let stages = [Stages<DXIL1_0, [all_stages]>];
|
|
let attributes = [Attributes<DXIL1_0, [ReadNone]>];
|
|
}
|
|
|
|
def WaveIsFirstLane : DXILOp<110, waveIsFirstLane> {
|
|
let Doc = "returns 1 for the first lane in the wave";
|
|
let intrinsics = [IntrinSelect<int_dx_wave_is_first_lane>];
|
|
let arguments = [];
|
|
let result = Int1Ty;
|
|
let stages = [Stages<DXIL1_0, [all_stages]>];
|
|
}
|
|
|
|
def WaveGetLaneIndex : DXILOp<111, waveGetLaneIndex> {
|
|
let Doc = "returns the index of the current lane in the wave";
|
|
let intrinsics = [IntrinSelect<int_dx_wave_getlaneindex>];
|
|
let arguments = [];
|
|
let result = Int32Ty;
|
|
let stages = [Stages<DXIL1_0, [all_stages]>];
|
|
let attributes = [Attributes<DXIL1_0, [ReadOnly]>];
|
|
}
|
|
|
|
def WaveActiveAnyTrue : DXILOp<113, waveAnyTrue> {
|
|
let Doc = "returns true if the expression is true in any of the active lanes "
|
|
"in the current wave";
|
|
let intrinsics = [IntrinSelect<int_dx_wave_any>];
|
|
let arguments = [Int1Ty];
|
|
let result = Int1Ty;
|
|
let stages = [Stages<DXIL1_0, [all_stages]>];
|
|
}
|
|
|
|
def WaveActiveAllTrue : DXILOp<114, waveAllTrue> {
|
|
let Doc = "returns true if the expression is true in all of the active lanes "
|
|
"in the current wave";
|
|
let intrinsics = [IntrinSelect<int_dx_wave_all>];
|
|
let arguments = [Int1Ty];
|
|
let result = Int1Ty;
|
|
let stages = [Stages<DXIL1_0, [all_stages]>];
|
|
}
|
|
|
|
def WaveReadLaneAt : DXILOp<117, waveReadLaneAt> {
|
|
let Doc = "returns the value from the specified lane";
|
|
let intrinsics = [IntrinSelect<int_dx_wave_readlane>];
|
|
let arguments = [OverloadTy, Int32Ty];
|
|
let result = OverloadTy;
|
|
let overloads = [Overloads<
|
|
DXIL1_0, [HalfTy, FloatTy, DoubleTy, Int1Ty, Int16Ty, Int32Ty, Int64Ty]>];
|
|
let stages = [Stages<DXIL1_0, [all_stages]>];
|
|
}
|
|
|
|
def WaveActiveOp : DXILOp<119, waveActiveOp> {
|
|
let Doc = "returns the result of the operation across waves";
|
|
let intrinsics = [
|
|
IntrinSelect<int_dx_wave_reduce_sum,
|
|
[
|
|
IntrinArgIndex<0>, IntrinArgI8<WaveOpKind_Sum>,
|
|
IntrinArgI8<SignedOpKind_Signed>
|
|
]>,
|
|
IntrinSelect<int_dx_wave_reduce_usum,
|
|
[
|
|
IntrinArgIndex<0>, IntrinArgI8<WaveOpKind_Sum>,
|
|
IntrinArgI8<SignedOpKind_Unsigned>
|
|
]>,
|
|
IntrinSelect<int_dx_wave_reduce_max,
|
|
[
|
|
IntrinArgIndex<0>, IntrinArgI8<WaveOpKind_Max>,
|
|
IntrinArgI8<SignedOpKind_Signed>
|
|
]>,
|
|
IntrinSelect<int_dx_wave_reduce_umax,
|
|
[
|
|
IntrinArgIndex<0>, IntrinArgI8<WaveOpKind_Max>,
|
|
IntrinArgI8<SignedOpKind_Unsigned>
|
|
]>,
|
|
];
|
|
|
|
let arguments = [OverloadTy, Int8Ty, Int8Ty];
|
|
let result = OverloadTy;
|
|
let overloads = [
|
|
Overloads<DXIL1_0, [HalfTy, FloatTy, DoubleTy, Int16Ty, Int32Ty, Int64Ty]>
|
|
];
|
|
let stages = [Stages<DXIL1_0, [all_stages]>];
|
|
let attributes = [Attributes<DXIL1_0, []>];
|
|
}
|
|
|
|
def WaveAllBitCount : DXILOp<135, waveAllOp> {
|
|
let Doc = "returns the count of bits set to 1 across the wave";
|
|
let intrinsics = [IntrinSelect<int_dx_wave_active_countbits>];
|
|
let arguments = [Int1Ty];
|
|
let result = Int32Ty;
|
|
let stages = [Stages<DXIL1_0, [all_stages]>];
|
|
}
|
|
|
|
def RawBufferLoad : DXILOp<139, rawBufferLoad> {
|
|
let Doc = "reads from a raw buffer and structured buffer";
|
|
// Handle, Coord0, Coord1, Mask, Alignment
|
|
let arguments = [HandleTy, Int32Ty, Int32Ty, Int8Ty, Int32Ty];
|
|
let result = OverloadTy;
|
|
let overloads = [
|
|
Overloads<DXIL1_2,
|
|
[ResRetHalfTy, ResRetFloatTy, ResRetInt16Ty, ResRetInt32Ty]>,
|
|
Overloads<DXIL1_3,
|
|
[
|
|
ResRetHalfTy, ResRetFloatTy, ResRetDoubleTy, ResRetInt16Ty,
|
|
ResRetInt32Ty, ResRetInt64Ty
|
|
]>
|
|
];
|
|
let stages = [Stages<DXIL1_2, [all_stages]>];
|
|
}
|
|
|
|
def RawBufferStore : DXILOp<140, rawBufferStore> {
|
|
let Doc = "writes to a RWByteAddressBuffer or RWStructuredBuffer";
|
|
// Handle, Coord0, Coord1, Val0, Val1, Val2, Val3, Mask, Alignment
|
|
let arguments = [
|
|
HandleTy, Int32Ty, Int32Ty, OverloadTy, OverloadTy, OverloadTy, OverloadTy,
|
|
Int8Ty, Int32Ty
|
|
];
|
|
let result = VoidTy;
|
|
let overloads = [
|
|
Overloads<DXIL1_2,
|
|
[ResRetHalfTy, ResRetFloatTy, ResRetInt16Ty, ResRetInt32Ty]>,
|
|
Overloads<DXIL1_3,
|
|
[
|
|
ResRetHalfTy, ResRetFloatTy, ResRetDoubleTy, ResRetInt16Ty,
|
|
ResRetInt32Ty, ResRetInt64Ty
|
|
]>
|
|
];
|
|
let stages = [Stages<DXIL1_2, [all_stages]>];
|
|
}
|
|
|
|
def Dot2AddHalf : DXILOp<162, dot2AddHalf> {
|
|
let Doc = "2D half dot product with accumulate to float";
|
|
let intrinsics = [IntrinSelect<int_dx_dot2add>];
|
|
let arguments = [FloatTy, HalfTy, HalfTy, HalfTy, HalfTy];
|
|
let result = FloatTy;
|
|
let overloads = [Overloads<DXIL1_0, []>];
|
|
let stages = [Stages<DXIL1_0, [all_stages]>];
|
|
let attributes = [Attributes<DXIL1_0, [ReadNone]>];
|
|
}
|
|
|
|
def Dot4AddI8Packed : DXILOp<163, dot4AddPacked> {
|
|
let Doc = "signed dot product of 4 x i8 vectors packed into i32, with "
|
|
"accumulate to i32";
|
|
let intrinsics = [IntrinSelect<int_dx_dot4add_i8packed>];
|
|
let arguments = [Int32Ty, Int32Ty, Int32Ty];
|
|
let result = Int32Ty;
|
|
let stages = [Stages<DXIL1_0, [all_stages]>];
|
|
let attributes = [Attributes<DXIL1_0, [ReadNone]>];
|
|
}
|
|
|
|
def Dot4AddU8Packed : DXILOp<164, dot4AddPacked> {
|
|
let Doc = "unsigned dot product of 4 x i8 vectors packed into i32, with "
|
|
"accumulate to i32";
|
|
let intrinsics = [IntrinSelect<int_dx_dot4add_u8packed>];
|
|
let arguments = [Int32Ty, Int32Ty, Int32Ty];
|
|
let result = Int32Ty;
|
|
let stages = [Stages<DXIL1_0, [all_stages]>];
|
|
let attributes = [Attributes<DXIL1_0, [ReadNone]>];
|
|
}
|
|
|
|
def AnnotateHandle : DXILOp<216, annotateHandle> {
|
|
let Doc = "annotate handle with resource properties";
|
|
let arguments = [HandleTy, ResPropsTy];
|
|
let result = HandleTy;
|
|
let stages = [Stages<DXIL1_6, [all_stages]>];
|
|
let attributes = [Attributes<DXIL1_0, [ReadNone]>];
|
|
}
|
|
|
|
def CreateHandleFromBinding : DXILOp<217, createHandleFromBinding> {
|
|
let Doc = "create resource handle from binding";
|
|
let arguments = [ResBindTy, Int32Ty, Int1Ty];
|
|
let result = HandleTy;
|
|
let stages = [Stages<DXIL1_6, [all_stages]>];
|
|
let attributes = [Attributes<DXIL1_0, [ReadNone]>];
|
|
}
|