Sameer Sahasrabuddhe 0807e94951 revert changes from r342722 ...

"[AMDGPU] lower-switch in preISel as a workaround for legacy DA"

This broke regression tests. The first breakage was noticed here:
http://lab.llvm.org:8011/builders/lld-x86_64-freebsd/builds/23549

llvm-svn: 342743

2018-09-21 16:31:51 +00:00

..

AArch64

[NFC][x86][AArch64] Add BEXTR-like test patterns.

2018-09-20 07:54:49 +00:00

AMDGPU

revert changes from r342722

2018-09-21 16:31:51 +00:00

ARC

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ARM

[ARM] Fix unwind information for floating point registers

2018-09-19 13:25:31 +00:00

AVR

[AVR] Redefine the 'LSL' instruction as an alias of 'ADD'

2018-09-01 12:23:00 +00:00

BPF

bpf: check illegal usage of XADD insn return value

2018-09-20 22:24:27 +00:00

Generic

[MC/Dwarf] Unclamp DWARF linetables format on Darwin.

2018-09-13 13:13:50 +00:00

Hexagon

[MachineVerifier] Relax checkLivenessAtDef regarding dead subreg defs

2018-09-20 06:59:18 +00:00

Inputs

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Lanai

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Mips

[mips][microMIPS] Extending size reduction pass with MOVEP

2018-09-19 18:46:29 +00:00

MIR

add IR flags to MI

2018-09-11 21:35:32 +00:00

MSP430

[DAGCombiner] Add X / X -> 1 & X % X -> 0 folds (test tweaks)

2018-08-29 11:18:14 +00:00

Nios2

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NVPTX

[NVPTX] Implement isLegalToVectorizeLoadChain

2018-08-27 17:29:43 +00:00

PowerPC

[PowerPC] Fix the assert of combineBVOfConsecutiveLoads when element num is 1

2018-09-20 03:09:15 +00:00

RISCV

[RISCV] Codegen for i8, i16, and i32 atomicrmw with RV32A

2018-09-19 10:54:22 +00:00

SPARC

[Sparc] Use ANDN instead of AND if constant can be encoded more efficiently

2018-08-30 14:05:26 +00:00

SystemZ

[DAGCombiner] Add X / X -> 1 & X % X -> 0 folds (test tweaks)

2018-08-29 11:18:14 +00:00

Thumb

CodeGen: Make computeRegisterLiveness search forward first

2018-08-30 07:18:10 +00:00

Thumb2

Work around grep vs. CRLF issue in Thumb2 test by matching excess whitespace

2018-09-18 00:04:29 +00:00

WebAssembly

[WebAssembly][NFC] Add missing tests for indirect calls

2018-09-20 22:08:27 +00:00

WinCFGuard

[COFF] Emit @feat.00 on 64-bit and set the CFG bit when emitting guardcf tables

2018-09-19 09:58:30 +00:00

WinEH

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X86

[X86][Sched] Add zero idiom sched data to the SNB model.

2018-09-21 14:07:20 +00:00

XCore

[DAGCombiner] extend(ifpositive(X)) -> shift-right (not X)

2018-07-15 16:27:07 +00:00