921d43fbb2
This patch fills holes in executable sections with 0xd4 (ARM) or 0xef (MIPS). These trap instructions were suggested by Theo de Raadt. llvm-svn: 306322
424 lines
14 KiB
C++
424 lines
14 KiB
C++
//===- MIPS.cpp -----------------------------------------------------------===//
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//
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// The LLVM Linker
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "Error.h"
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#include "InputFiles.h"
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#include "OutputSections.h"
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#include "Symbols.h"
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#include "SyntheticSections.h"
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#include "Target.h"
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#include "Thunks.h"
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#include "llvm/Object/ELF.h"
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#include "llvm/Support/Endian.h"
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using namespace llvm;
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using namespace llvm::object;
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using namespace llvm::support::endian;
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using namespace llvm::ELF;
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using namespace lld;
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using namespace lld::elf;
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namespace {
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template <class ELFT> class MIPS final : public TargetInfo {
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public:
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MIPS();
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RelExpr getRelExpr(uint32_t Type, const SymbolBody &S,
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const uint8_t *Loc) const override;
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int64_t getImplicitAddend(const uint8_t *Buf, uint32_t Type) const override;
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bool isPicRel(uint32_t Type) const override;
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uint32_t getDynRel(uint32_t Type) const override;
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void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const override;
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void writePltHeader(uint8_t *Buf) const override;
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void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr,
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int32_t Index, unsigned RelOff) const override;
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bool needsThunk(RelExpr Expr, uint32_t RelocType, const InputFile *File,
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const SymbolBody &S) const override;
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void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
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bool usesOnlyLowPageBits(uint32_t Type) const override;
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};
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} // namespace
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template <class ELFT> MIPS<ELFT>::MIPS() {
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GotPltHeaderEntriesNum = 2;
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DefaultMaxPageSize = 65536;
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GotEntrySize = sizeof(typename ELFT::uint);
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GotPltEntrySize = sizeof(typename ELFT::uint);
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PltEntrySize = 16;
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PltHeaderSize = 32;
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CopyRel = R_MIPS_COPY;
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PltRel = R_MIPS_JUMP_SLOT;
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NeedsThunks = true;
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TrapInstr = 0xefefefef;
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if (ELFT::Is64Bits) {
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RelativeRel = (R_MIPS_64 << 8) | R_MIPS_REL32;
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TlsGotRel = R_MIPS_TLS_TPREL64;
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TlsModuleIndexRel = R_MIPS_TLS_DTPMOD64;
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TlsOffsetRel = R_MIPS_TLS_DTPREL64;
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} else {
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RelativeRel = R_MIPS_REL32;
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TlsGotRel = R_MIPS_TLS_TPREL32;
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TlsModuleIndexRel = R_MIPS_TLS_DTPMOD32;
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TlsOffsetRel = R_MIPS_TLS_DTPREL32;
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}
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}
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template <class ELFT>
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RelExpr MIPS<ELFT>::getRelExpr(uint32_t Type, const SymbolBody &S,
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const uint8_t *Loc) const {
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// See comment in the calculateMipsRelChain.
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if (ELFT::Is64Bits || Config->MipsN32Abi)
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Type &= 0xff;
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switch (Type) {
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default:
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return R_ABS;
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case R_MIPS_JALR:
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return R_HINT;
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case R_MIPS_GPREL16:
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case R_MIPS_GPREL32:
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return R_MIPS_GOTREL;
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case R_MIPS_26:
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return R_PLT;
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case R_MIPS_HI16:
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case R_MIPS_LO16:
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// R_MIPS_HI16/R_MIPS_LO16 relocations against _gp_disp calculate
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// offset between start of function and 'gp' value which by default
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// equal to the start of .got section. In that case we consider these
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// relocations as relative.
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if (&S == ElfSym::MipsGpDisp)
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return R_MIPS_GOT_GP_PC;
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if (&S == ElfSym::MipsLocalGp)
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return R_MIPS_GOT_GP;
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LLVM_FALLTHROUGH;
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case R_MIPS_GOT_OFST:
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return R_ABS;
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case R_MIPS_PC32:
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case R_MIPS_PC16:
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case R_MIPS_PC19_S2:
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case R_MIPS_PC21_S2:
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case R_MIPS_PC26_S2:
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case R_MIPS_PCHI16:
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case R_MIPS_PCLO16:
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return R_PC;
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case R_MIPS_GOT16:
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if (S.isLocal())
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return R_MIPS_GOT_LOCAL_PAGE;
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LLVM_FALLTHROUGH;
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case R_MIPS_CALL16:
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case R_MIPS_GOT_DISP:
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case R_MIPS_TLS_GOTTPREL:
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return R_MIPS_GOT_OFF;
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case R_MIPS_CALL_HI16:
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case R_MIPS_CALL_LO16:
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case R_MIPS_GOT_HI16:
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case R_MIPS_GOT_LO16:
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return R_MIPS_GOT_OFF32;
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case R_MIPS_GOT_PAGE:
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return R_MIPS_GOT_LOCAL_PAGE;
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case R_MIPS_TLS_GD:
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return R_MIPS_TLSGD;
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case R_MIPS_TLS_LDM:
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return R_MIPS_TLSLD;
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}
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}
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template <class ELFT> bool MIPS<ELFT>::isPicRel(uint32_t Type) const {
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return Type == R_MIPS_32 || Type == R_MIPS_64;
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}
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template <class ELFT> uint32_t MIPS<ELFT>::getDynRel(uint32_t Type) const {
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return RelativeRel;
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}
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template <class ELFT>
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void MIPS<ELFT>::writeGotPlt(uint8_t *Buf, const SymbolBody &) const {
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write32<ELFT::TargetEndianness>(Buf, InX::Plt->getVA());
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}
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template <endianness E, uint8_t BSIZE, uint8_t SHIFT>
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static int64_t getPcRelocAddend(const uint8_t *Loc) {
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uint32_t Instr = read32<E>(Loc);
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uint32_t Mask = 0xffffffff >> (32 - BSIZE);
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return SignExtend64<BSIZE + SHIFT>((Instr & Mask) << SHIFT);
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}
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template <endianness E, uint8_t BSIZE, uint8_t SHIFT>
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static void applyMipsPcReloc(uint8_t *Loc, uint32_t Type, uint64_t V) {
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uint32_t Mask = 0xffffffff >> (32 - BSIZE);
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uint32_t Instr = read32<E>(Loc);
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if (SHIFT > 0)
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checkAlignment<(1 << SHIFT)>(Loc, V, Type);
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checkInt<BSIZE + SHIFT>(Loc, V, Type);
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write32<E>(Loc, (Instr & ~Mask) | ((V >> SHIFT) & Mask));
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}
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template <endianness E> static void writeMipsHi16(uint8_t *Loc, uint64_t V) {
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uint32_t Instr = read32<E>(Loc);
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uint16_t Res = ((V + 0x8000) >> 16) & 0xffff;
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write32<E>(Loc, (Instr & 0xffff0000) | Res);
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}
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template <endianness E> static void writeMipsHigher(uint8_t *Loc, uint64_t V) {
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uint32_t Instr = read32<E>(Loc);
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uint16_t Res = ((V + 0x80008000) >> 32) & 0xffff;
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write32<E>(Loc, (Instr & 0xffff0000) | Res);
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}
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template <endianness E> static void writeMipsHighest(uint8_t *Loc, uint64_t V) {
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uint32_t Instr = read32<E>(Loc);
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uint16_t Res = ((V + 0x800080008000) >> 48) & 0xffff;
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write32<E>(Loc, (Instr & 0xffff0000) | Res);
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}
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template <endianness E> static void writeMipsLo16(uint8_t *Loc, uint64_t V) {
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uint32_t Instr = read32<E>(Loc);
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write32<E>(Loc, (Instr & 0xffff0000) | (V & 0xffff));
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}
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template <class ELFT> static bool isMipsR6() {
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const auto &FirstObj = cast<ELFFileBase<ELFT>>(*Config->FirstElf);
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uint32_t Arch = FirstObj.getObj().getHeader()->e_flags & EF_MIPS_ARCH;
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return Arch == EF_MIPS_ARCH_32R6 || Arch == EF_MIPS_ARCH_64R6;
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}
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template <class ELFT> void MIPS<ELFT>::writePltHeader(uint8_t *Buf) const {
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const endianness E = ELFT::TargetEndianness;
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if (Config->MipsN32Abi) {
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write32<E>(Buf, 0x3c0e0000); // lui $14, %hi(&GOTPLT[0])
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write32<E>(Buf + 4, 0x8dd90000); // lw $25, %lo(&GOTPLT[0])($14)
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write32<E>(Buf + 8, 0x25ce0000); // addiu $14, $14, %lo(&GOTPLT[0])
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write32<E>(Buf + 12, 0x030ec023); // subu $24, $24, $14
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} else {
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write32<E>(Buf, 0x3c1c0000); // lui $28, %hi(&GOTPLT[0])
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write32<E>(Buf + 4, 0x8f990000); // lw $25, %lo(&GOTPLT[0])($28)
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write32<E>(Buf + 8, 0x279c0000); // addiu $28, $28, %lo(&GOTPLT[0])
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write32<E>(Buf + 12, 0x031cc023); // subu $24, $24, $28
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}
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write32<E>(Buf + 16, 0x03e07825); // move $15, $31
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write32<E>(Buf + 20, 0x0018c082); // srl $24, $24, 2
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write32<E>(Buf + 24, 0x0320f809); // jalr $25
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write32<E>(Buf + 28, 0x2718fffe); // subu $24, $24, 2
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uint64_t GotPlt = InX::GotPlt->getVA();
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writeMipsHi16<E>(Buf, GotPlt);
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writeMipsLo16<E>(Buf + 4, GotPlt);
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writeMipsLo16<E>(Buf + 8, GotPlt);
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}
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template <class ELFT>
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void MIPS<ELFT>::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr,
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uint64_t PltEntryAddr, int32_t Index,
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unsigned RelOff) const {
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const endianness E = ELFT::TargetEndianness;
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write32<E>(Buf, 0x3c0f0000); // lui $15, %hi(.got.plt entry)
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write32<E>(Buf + 4, 0x8df90000); // l[wd] $25, %lo(.got.plt entry)($15)
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// jr $25
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write32<E>(Buf + 8, isMipsR6<ELFT>() ? 0x03200009 : 0x03200008);
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write32<E>(Buf + 12, 0x25f80000); // addiu $24, $15, %lo(.got.plt entry)
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writeMipsHi16<E>(Buf, GotPltEntryAddr);
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writeMipsLo16<E>(Buf + 4, GotPltEntryAddr);
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writeMipsLo16<E>(Buf + 12, GotPltEntryAddr);
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}
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template <class ELFT>
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bool MIPS<ELFT>::needsThunk(RelExpr Expr, uint32_t Type, const InputFile *File,
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const SymbolBody &S) const {
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// Any MIPS PIC code function is invoked with its address in register $t9.
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// So if we have a branch instruction from non-PIC code to the PIC one
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// we cannot make the jump directly and need to create a small stubs
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// to save the target function address.
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// See page 3-38 ftp://www.linux-mips.org/pub/linux/mips/doc/ABI/mipsabi.pdf
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if (Type != R_MIPS_26)
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return false;
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auto *F = dyn_cast_or_null<ELFFileBase<ELFT>>(File);
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if (!F)
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return false;
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// If current file has PIC code, LA25 stub is not required.
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if (F->getObj().getHeader()->e_flags & EF_MIPS_PIC)
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return false;
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auto *D = dyn_cast<DefinedRegular>(&S);
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// LA25 is required if target file has PIC code
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// or target symbol is a PIC symbol.
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return D && D->isMipsPIC<ELFT>();
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}
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template <class ELFT>
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int64_t MIPS<ELFT>::getImplicitAddend(const uint8_t *Buf, uint32_t Type) const {
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const endianness E = ELFT::TargetEndianness;
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switch (Type) {
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default:
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return 0;
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case R_MIPS_32:
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case R_MIPS_GPREL32:
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case R_MIPS_TLS_DTPREL32:
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case R_MIPS_TLS_TPREL32:
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return SignExtend64<32>(read32<E>(Buf));
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case R_MIPS_26:
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// FIXME (simon): If the relocation target symbol is not a PLT entry
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// we should use another expression for calculation:
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// ((A << 2) | (P & 0xf0000000)) >> 2
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return SignExtend64<28>((read32<E>(Buf) & 0x3ffffff) << 2);
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case R_MIPS_GPREL16:
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case R_MIPS_LO16:
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case R_MIPS_PCLO16:
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case R_MIPS_TLS_DTPREL_HI16:
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case R_MIPS_TLS_DTPREL_LO16:
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case R_MIPS_TLS_TPREL_HI16:
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case R_MIPS_TLS_TPREL_LO16:
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return SignExtend64<16>(read32<E>(Buf));
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case R_MIPS_PC16:
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return getPcRelocAddend<E, 16, 2>(Buf);
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case R_MIPS_PC19_S2:
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return getPcRelocAddend<E, 19, 2>(Buf);
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case R_MIPS_PC21_S2:
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return getPcRelocAddend<E, 21, 2>(Buf);
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case R_MIPS_PC26_S2:
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return getPcRelocAddend<E, 26, 2>(Buf);
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case R_MIPS_PC32:
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return getPcRelocAddend<E, 32, 0>(Buf);
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}
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}
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static std::pair<uint32_t, uint64_t>
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calculateMipsRelChain(uint8_t *Loc, uint32_t Type, uint64_t Val) {
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// MIPS N64 ABI packs multiple relocations into the single relocation
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// record. In general, all up to three relocations can have arbitrary
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// types. In fact, Clang and GCC uses only a few combinations. For now,
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// we support two of them. That is allow to pass at least all LLVM
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// test suite cases.
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// <any relocation> / R_MIPS_SUB / R_MIPS_HI16 | R_MIPS_LO16
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// <any relocation> / R_MIPS_64 / R_MIPS_NONE
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// The first relocation is a 'real' relocation which is calculated
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// using the corresponding symbol's value. The second and the third
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// relocations used to modify result of the first one: extend it to
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// 64-bit, extract high or low part etc. For details, see part 2.9 Relocation
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// at the https://dmz-portal.mips.com/mw/images/8/82/007-4658-001.pdf
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uint32_t Type2 = (Type >> 8) & 0xff;
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uint32_t Type3 = (Type >> 16) & 0xff;
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if (Type2 == R_MIPS_NONE && Type3 == R_MIPS_NONE)
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return std::make_pair(Type, Val);
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if (Type2 == R_MIPS_64 && Type3 == R_MIPS_NONE)
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return std::make_pair(Type2, Val);
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if (Type2 == R_MIPS_SUB && (Type3 == R_MIPS_HI16 || Type3 == R_MIPS_LO16))
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return std::make_pair(Type3, -Val);
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error(getErrorLocation(Loc) + "unsupported relocations combination " +
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Twine(Type));
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return std::make_pair(Type & 0xff, Val);
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}
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template <class ELFT>
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void MIPS<ELFT>::relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const {
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const endianness E = ELFT::TargetEndianness;
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// Thread pointer and DRP offsets from the start of TLS data area.
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// https://www.linux-mips.org/wiki/NPTL
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if (Type == R_MIPS_TLS_DTPREL_HI16 || Type == R_MIPS_TLS_DTPREL_LO16 ||
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Type == R_MIPS_TLS_DTPREL32 || Type == R_MIPS_TLS_DTPREL64)
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Val -= 0x8000;
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else if (Type == R_MIPS_TLS_TPREL_HI16 || Type == R_MIPS_TLS_TPREL_LO16 ||
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Type == R_MIPS_TLS_TPREL32 || Type == R_MIPS_TLS_TPREL64)
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Val -= 0x7000;
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if (ELFT::Is64Bits || Config->MipsN32Abi)
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std::tie(Type, Val) = calculateMipsRelChain(Loc, Type, Val);
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switch (Type) {
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case R_MIPS_32:
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case R_MIPS_GPREL32:
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case R_MIPS_TLS_DTPREL32:
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case R_MIPS_TLS_TPREL32:
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write32<E>(Loc, Val);
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break;
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case R_MIPS_64:
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case R_MIPS_TLS_DTPREL64:
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case R_MIPS_TLS_TPREL64:
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write64<E>(Loc, Val);
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break;
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case R_MIPS_26:
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write32<E>(Loc, (read32<E>(Loc) & ~0x3ffffff) | ((Val >> 2) & 0x3ffffff));
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break;
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case R_MIPS_GOT16:
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// The R_MIPS_GOT16 relocation's value in "relocatable" linking mode
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// is updated addend (not a GOT index). In that case write high 16 bits
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// to store a correct addend value.
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if (Config->Relocatable)
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writeMipsHi16<E>(Loc, Val);
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else {
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checkInt<16>(Loc, Val, Type);
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writeMipsLo16<E>(Loc, Val);
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}
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break;
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case R_MIPS_GOT_DISP:
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case R_MIPS_GOT_PAGE:
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case R_MIPS_GPREL16:
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case R_MIPS_TLS_GD:
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case R_MIPS_TLS_LDM:
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checkInt<16>(Loc, Val, Type);
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LLVM_FALLTHROUGH;
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case R_MIPS_CALL16:
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case R_MIPS_CALL_LO16:
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case R_MIPS_GOT_LO16:
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case R_MIPS_GOT_OFST:
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case R_MIPS_LO16:
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case R_MIPS_PCLO16:
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case R_MIPS_TLS_DTPREL_LO16:
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case R_MIPS_TLS_GOTTPREL:
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case R_MIPS_TLS_TPREL_LO16:
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writeMipsLo16<E>(Loc, Val);
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break;
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case R_MIPS_CALL_HI16:
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case R_MIPS_GOT_HI16:
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case R_MIPS_HI16:
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case R_MIPS_PCHI16:
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case R_MIPS_TLS_DTPREL_HI16:
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case R_MIPS_TLS_TPREL_HI16:
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writeMipsHi16<E>(Loc, Val);
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break;
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case R_MIPS_HIGHER:
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writeMipsHigher<E>(Loc, Val);
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break;
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case R_MIPS_HIGHEST:
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writeMipsHighest<E>(Loc, Val);
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break;
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case R_MIPS_JALR:
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// Ignore this optimization relocation for now
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break;
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case R_MIPS_PC16:
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applyMipsPcReloc<E, 16, 2>(Loc, Type, Val);
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break;
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case R_MIPS_PC19_S2:
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applyMipsPcReloc<E, 19, 2>(Loc, Type, Val);
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break;
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case R_MIPS_PC21_S2:
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applyMipsPcReloc<E, 21, 2>(Loc, Type, Val);
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break;
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case R_MIPS_PC26_S2:
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applyMipsPcReloc<E, 26, 2>(Loc, Type, Val);
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break;
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case R_MIPS_PC32:
|
|
applyMipsPcReloc<E, 32, 0>(Loc, Type, Val);
|
|
break;
|
|
default:
|
|
error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type));
|
|
}
|
|
}
|
|
|
|
template <class ELFT>
|
|
bool MIPS<ELFT>::usesOnlyLowPageBits(uint32_t Type) const {
|
|
return Type == R_MIPS_LO16 || Type == R_MIPS_GOT_OFST;
|
|
}
|
|
|
|
template <class ELFT> TargetInfo *elf::getMipsTargetInfo() {
|
|
static MIPS<ELFT> Target;
|
|
return &Target;
|
|
}
|
|
|
|
template TargetInfo *elf::getMipsTargetInfo<ELF32LE>();
|
|
template TargetInfo *elf::getMipsTargetInfo<ELF32BE>();
|
|
template TargetInfo *elf::getMipsTargetInfo<ELF64LE>();
|
|
template TargetInfo *elf::getMipsTargetInfo<ELF64BE>();
|