llvm-project

AsmParser

[RISCV][MC] Introduce XSfvfexp* and XSfvfbfexpa* extensions and their MC supports (#164349 )

2025-10-21 18:27:21 -07:00

Disassembler

[RISCV][MC] Introduce XSfvfexp* and XSfvfbfexpa* extensions and their MC supports (#164349 )

2025-10-21 18:27:21 -07:00

GISel

[RISCV][GISel] Support select vector store instrinsics (#165500 )

2025-10-31 14:42:56 +08:00

MCA

[Target] Add "override" where appropriate (NFC) (#165083 )

2025-10-25 06:23:43 -07:00

MCTargetDesc

[RISCV] fixup_riscv_rvc_imm may be linker relaxable (#161797 )

2025-10-28 10:35:36 -07:00

TargetInfo

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CMakeLists.txt

Recommit "[RISCV] Don't run loop-idiom-vectorize pass in the O0 pipeline. (#156798 )"

2025-09-04 09:50:12 -07:00

RISCV.h

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RISCV.td

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RISCVAsmPrinter.cpp

[RISCV] Support XSfmm LLVM IR and CodeGen (#143069 )

2025-10-14 02:01:57 +00:00

RISCVCallingConv.cpp

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RISCVCallingConv.h

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RISCVCallingConv.td

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RISCVCodeGenPrepare.cpp

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RISCVCombine.td

[RISCV][GISel] Fold G_FCONSTANT 0.0 store into G_CONSTANT x0 (#163008 )

2025-10-23 15:50:04 +08:00

RISCVConstantPoolValue.cpp

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RISCVConstantPoolValue.h

[Target] Add "override" where appropriate (NFC) (#165083 )

2025-10-25 06:23:43 -07:00

RISCVDeadRegisterDefinitions.cpp

CodeGen: Remove MachineFunction argument from getRegClass (#158188 )

2025-09-12 19:22:02 +09:00

RISCVExpandAtomicPseudoInsts.cpp

[RISCV] 'Zalrsc' may permit non-base instructions (#165042 )

2025-10-28 12:51:11 -07:00

RISCVExpandPseudoInsts.cpp

[RISCV] Add short forward branch support for min, max, maxu and minu (#164394 )

2025-10-31 10:19:25 +05:30

RISCVFeatures.td

[RISCV] Add short forward branch support for min, max, maxu and minu (#164394 )

2025-10-31 10:19:25 +05:30

RISCVFoldMemOffset.cpp

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RISCVFrameLowering.cpp

[RISCV] Replace uses of RISCV::NoRegister with Register() or isValid. NFC (#161781 )

2025-10-03 08:53:58 -07:00

RISCVFrameLowering.h

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RISCVGatherScatterLowering.cpp

[IR] Replace alignment argument with attribute on masked intrinsics (#163802 )

2025-10-20 08:50:09 +00:00

RISCVGISel.td

[RISCV][GISel] Add manual isel for s8/s16/s32 load/store for the GPR bank. (#161995 )

2025-10-07 21:30:09 -07:00

RISCVIndirectBranchTracking.cpp

[RISCV][NFC] Fix typo in RISCVIndirectBranchTracking.cpp (#157221 )

2025-09-08 15:02:48 +08:00

RISCVInsertReadWriteCSR.cpp

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RISCVInsertVSETVLI.cpp

[RISCV] Support Zvfbfa codegen (#161158 )

2025-10-18 15:22:21 +00:00

RISCVInsertWriteVXRM.cpp

[llvm] Use "= default" (NFC) (#166088 )

2025-11-02 17:16:47 -08:00

RISCVInstrFormats.td

[RISCV] Use a tablegen class for AltFmtType. NFC (#163251 )

2025-10-13 23:19:23 -07:00

RISCVInstrFormatsC.td

[RISCV] Remove post-decoding instruction adjustments (#156360 )

2025-09-04 16:02:34 +00:00

RISCVInstrFormatsV.td

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RISCVInstrGISel.td

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RISCVInstrInfo.cpp

[RISCV] Mask integer and float loads as canFoldAsLoad for stackmaps (#165761 )

2025-10-31 14:42:16 +00:00

RISCVInstrInfo.h

[RISCV][NFC] Avoid iteration and division while selecting SHXADD instructions (#158851 )

2025-10-07 07:26:41 +02:00

RISCVInstrInfo.td

[RISCV] Mask integer and float loads as canFoldAsLoad for stackmaps (#165761 )

2025-10-31 14:42:16 +00:00

RISCVInstrInfoA.td

[RISCV][LLVM] Enable atomics for 'Zalrsc' (#163672 )

2025-10-21 09:33:19 -07:00

RISCVInstrInfoC.td

[TableGen][DecoderEmitter][RISCV] Always handle bits<0> (#159951 )

2025-09-22 20:50:17 +03:00

RISCVInstrInfoD.td

[RISCV] Mask integer and float loads as canFoldAsLoad for stackmaps (#165761 )

2025-10-31 14:42:16 +00:00

RISCVInstrInfoF.td

[RISCV] Mask integer and float loads as canFoldAsLoad for stackmaps (#165761 )

2025-10-31 14:42:16 +00:00

RISCVInstrInfoM.td

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RISCVInstrInfoP.td

[RISCV] Support P extension ABSW instruction. (#165047 )

2025-10-30 08:42:38 -07:00

RISCVInstrInfoQ.td

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RISCVInstrInfoSFB.td

[RISCV] Add short forward branch support for min, max, maxu and minu (#164394 )

2025-10-31 10:19:25 +05:30

RISCVInstrInfoV.td

[NFC][RISCV] Move Zvfbf* relative stuffs to RISCVInstrInfoZvfbf.td (#159619 )

2025-09-19 23:57:59 +08:00

RISCVInstrInfoVPseudos.td

[RISCV] Move more stuff to RISCVInstrInfoZvfbf.td. Fix incorrect Predicates. (#163846 )

2025-10-16 21:26:34 -07:00

RISCVInstrInfoVSDPatterns.td

[RISCV] Rename BFloatVectors -> BF16Vectors in tablegen. NFC (#161469 )

2025-09-30 19:53:21 -07:00

RISCVInstrInfoVVLPatterns.td

[RISCV] Rename BFloatVectors -> BF16Vectors in tablegen. NFC (#161469 )

2025-09-30 19:53:21 -07:00

RISCVInstrInfoXAndes.td

[RISCV] Rename BFloatVectors -> BF16Vectors in tablegen. NFC (#161469 )

2025-09-30 19:53:21 -07:00

RISCVInstrInfoXCV.td

[RISCV] Use i32 in more RV32 only patterns. NFC

2025-10-11 09:57:10 -07:00

RISCVInstrInfoXMips.td

[RISCV] Add "MIPS" to name of MIPS-specific RISCVSubtarget functions. NFC (#162122 )

2025-10-06 11:33:20 -07:00

RISCVInstrInfoXqccmp.td

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RISCVInstrInfoXqci.td

[RISCV] Use i32 in more RV32 only patterns. NFC

2025-10-11 09:57:10 -07:00

RISCVInstrInfoXRivos.td

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RISCVInstrInfoXSf.td

[RISCV] Add LLVM IR intrinsics and codegen for XSfvfexp* and XSfvfexpa* (#164499 )

2025-10-24 18:09:03 +00:00

RISCVInstrInfoXSfmm.td

[RISCV] Support XSfmm LLVM IR and CodeGen (#143069 )

2025-10-14 02:01:57 +00:00

RISCVInstrInfoXSpacemiT.td

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RISCVInstrInfoXTHead.td

[RISCV] Remove a couple of custom instruction decoders (NFC) (#158483 )

2025-09-15 00:57:31 +03:00

RISCVInstrInfoXVentana.td

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RISCVInstrInfoXwch.td

[RISCV] Remove post-decoding instruction adjustments (#156360 )

2025-09-04 16:02:34 +00:00

RISCVInstrInfoZa.td

[RISCV] Reorder ins/outs of atomic instruction to match their assembly order. NFC (#162411 )

2025-10-07 22:24:52 -07:00

RISCVInstrInfoZalasr.td

[RISCV][GISel] Add manual isel for s8/s16/s32 load/store for the GPR bank. (#161995 )

2025-10-07 21:30:09 -07:00

RISCVInstrInfoZb.td

[RISCV] Support codegen for some scalar P extension instructions. (#164359 )

2025-10-24 18:20:53 +00:00

RISCVInstrInfoZc.td

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RISCVInstrInfoZclsd.td

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RISCVInstrInfoZcmop.td

[RISCV] Add underscores to instructions names for Zimop/Zcmop. (#155289 )

2025-08-25 14:06:28 -07:00

RISCVInstrInfoZfa.td

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RISCVInstrInfoZfbfmin.td

[RISCV] Add isel for bitcasting between bfloat and half types (#158828 )

2025-09-17 12:10:47 -07:00

RISCVInstrInfoZfh.td

[RISCV] Use i32 in more RV32 only patterns. NFC

2025-10-11 09:57:10 -07:00

RISCVInstrInfoZibi.td

[RISCV][CodeGen] Add CodeGen support of Zibi experimental extension (#146858 )

2025-09-18 11:03:48 +08:00

RISCVInstrInfoZicbo.td

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RISCVInstrInfoZicfiss.td

[RISCV] Remove a couple of custom instruction decoders (NFC) (#158483 )

2025-09-15 00:57:31 +03:00

RISCVInstrInfoZicond.td

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RISCVInstrInfoZilsd.td

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RISCVInstrInfoZimop.td

[RISCV] Add underscores to instructions names for Zimop/Zcmop. (#155289 )

2025-08-25 14:06:28 -07:00

RISCVInstrInfoZk.td

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RISCVInstrInfoZvfbf.td

[llvm][RISCV] Handle fpround and fpextend for zvfbfa without zvfbfmin (#164366 )

2025-10-23 10:52:56 +08:00

RISCVInstrInfoZvfofp8min.td

[RISCV] Implement MC support for Zvfofp8min extension (#157014 )

2025-09-19 07:49:31 +00:00

RISCVInstrInfoZvk.td

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RISCVInstrInfoZvqdotq.td

[RISCV] Support ZVqdot Codegen and C intrinsics (#154915 )

2025-09-05 11:38:58 +08:00

RISCVInstrPredicates.td

[RISCV] Add XSfmm pseudo instruction and vset* insertion support (#143068 )

2025-10-13 15:06:31 +00:00

RISCVInterleavedAccess.cpp

[IR] Replace alignment argument with attribute on masked intrinsics (#163802 )

2025-10-20 08:50:09 +00:00

RISCVISelDAGToDAG.cpp

[RISCV] Support P extension ABSW instruction. (#165047 )

2025-10-30 08:42:38 -07:00

RISCVISelDAGToDAG.h

[RISCV] Support XSfmm LLVM IR and CodeGen (#143069 )

2025-10-14 02:01:57 +00:00

RISCVISelLowering.cpp

[ADT] Prepare to deprecate variadic StringSwitch::Cases. NFC. (#166020 )

2025-11-02 00:12:33 +00:00

RISCVISelLowering.h

[RISCV][LLVM] Enable atomics for 'Zalrsc' (#163672 )

2025-10-21 09:33:19 -07:00

RISCVLandingPadSetup.cpp

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RISCVLateBranchOpt.cpp

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RISCVLoadStoreOptimizer.cpp

[RISCV] Add "MIPS" to name of MIPS-specific RISCVSubtarget functions. NFC (#162122 )

2025-10-06 11:33:20 -07:00

RISCVMachineFunctionInfo.cpp

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RISCVMachineFunctionInfo.h

[Target] Add "override" where appropriate (NFC) (#165083 )

2025-10-25 06:23:43 -07:00

RISCVMacroFusion.td

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RISCVMakeCompressible.cpp

[RISCV] Replace uses of RISCV::NoRegister with Register() or isValid. NFC (#161781 )

2025-10-03 08:53:58 -07:00

RISCVMergeBaseOffset.cpp

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RISCVMoveMerger.cpp

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RISCVOptWInstrs.cpp

[RISCV] Support P extension ABSW instruction. (#165047 )

2025-10-30 08:42:38 -07:00

RISCVPfmCounters.td

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RISCVPostRAExpandPseudoInsts.cpp

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RISCVProcessors.td

[RISCV] Toggle throttled FP64 feature in SiFive7 scheduling model with subtarget feature (#162400 )

2025-10-10 01:26:17 +00:00

RISCVProfiles.td

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RISCVPushPopOptimizer.cpp

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RISCVRedundantCopyElimination.cpp

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RISCVRegisterInfo.cpp

[RISCV] Reduce number of GPRs needed by lowerSegmentSpillReload. (#165337 )

2025-10-31 10:05:14 -07:00

RISCVRegisterInfo.h

CodeGen: Remove MachineFunction argument from getPointerRegClass (#158185 )

2025-09-12 09:18:50 +00:00

RISCVRegisterInfo.td

[RISCV] Remove i32 and i16 from GPR register class. NFC (#162425 )

2025-10-08 08:35:06 -07:00

RISCVSchedAndes45.td

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RISCVSchedGenericOOO.td

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RISCVSchedMIPSP8700.td

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RISCVSchedRocket.td

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RISCVSchedSiFive7.td

[RISCV] Add LLVM IR intrinsics and codegen for XSfvfexp* and XSfvfexpa* (#164499 )

2025-10-24 18:09:03 +00:00

RISCVSchedSiFiveP400.td

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RISCVSchedSiFiveP500.td

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RISCVSchedSiFiveP600.td

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RISCVSchedSiFiveP800.td

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RISCVSchedSpacemitX60.td

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RISCVSchedSyntacoreSCR1.td

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RISCVSchedSyntacoreSCR7.td

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RISCVSchedSyntacoreSCR345.td

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RISCVSchedTTAscalonD8.td

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RISCVSchedule.td

[RISCV] Add LLVM IR intrinsics and codegen for XSfvfexp* and XSfvfexpa* (#164499 )

2025-10-24 18:09:03 +00:00

RISCVScheduleV.td

[RISCV] Toggle throttled FP64 feature in SiFive7 scheduling model with subtarget feature (#162400 )

2025-10-10 01:26:17 +00:00

RISCVScheduleXSf.td

[RISCV] Add LLVM IR intrinsics and codegen for XSfvfexp* and XSfvfexpa* (#164499 )

2025-10-24 18:09:03 +00:00

RISCVScheduleZb.td

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RISCVScheduleZvk.td

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RISCVSchedXiangShanNanHu.td

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RISCVSelectionDAGInfo.cpp

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RISCVSelectionDAGInfo.h

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RISCVSubtarget.cpp

[RISCV] Add "MIPS" to name of MIPS-specific RISCVSubtarget functions. NFC (#162122 )

2025-10-06 11:33:20 -07:00

RISCVSubtarget.h

[RISCV] Support codegen for some scalar P extension instructions. (#164359 )

2025-10-24 18:20:53 +00:00

RISCVSystemOperands.td

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RISCVTargetMachine.cpp

[llvm] Make getEffectiveRelocModel helper consistent across targets. NFC (#165121 )

2025-10-25 21:20:20 -07:00

RISCVTargetMachine.h

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RISCVTargetObjectFile.cpp

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RISCVTargetObjectFile.h

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RISCVTargetTransformInfo.cpp

[ASan][RISCV] Support asan check for segment load/store RVV intrinsics. (#161317 )

2025-10-07 15:05:37 +08:00

RISCVTargetTransformInfo.h

Revert "[TTI][RISCV] Add cost modelling for intrinsic vp.load.ff (#160470 )"

2025-09-26 17:24:56 -07:00

RISCVVectorMaskDAGMutation.cpp

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RISCVVectorPeephole.cpp

[RISCV] Replace uses of RISCV::NoRegister with Register() or isValid. NFC (#161781 )

2025-10-03 08:53:58 -07:00

RISCVVLOptimizer.cpp

[llvm] Replace LLVM_ATTRIBUTE_UNUSED with [[maybe_unused]] (NFC) (#163330 )

2025-10-14 07:15:44 -07:00

RISCVVMV0Elimination.cpp

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RISCVZacasABIFix.cpp

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