Craig Topper 0ccbf91166 [RISCV] Remove Features from CPUInfo in RISCVTargetParser. ...

Instead of having separate feature bits, get information from march.
Invalid is now implied by empty march.
64-bit is now implied by march starting with "rv64".

Reviewed By: fpetrogalli

Differential Revision: https://reviews.llvm.org/D142230

2023-01-20 10:03:37 -08:00

..

Unix

…

Windows

…

AArch64TargetParser.cpp

[AArch64] Reland "Improve TargetParser API"

2023-01-14 14:43:38 +00:00

ARMTargetParser.cpp

…

ARMTargetParserCommon.cpp

…

CMakeLists.txt

[TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

2023-01-11 11:18:44 +01:00

CSKYTargetParser.cpp

…

Host.cpp

[X86] Support -march=emeraldrapids

2023-01-05 20:27:32 +08:00

LoongArchTargetParser.cpp

…

RISCVTargetParser.cpp

[RISCV] Remove Features from CPUInfo in RISCVTargetParser.

2023-01-20 10:03:37 -08:00

TargetParser.cpp

[TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

2023-01-11 11:18:44 +01:00

Triple.cpp

[Xtensa 1/10] Recognize Xtensa in triple parsing code

2022-12-26 13:30:51 +01:00

X86TargetParser.cpp

[X86] Support -march=emeraldrapids

2023-01-05 20:27:32 +08:00