86813aa786
Epilogue vectorization currently relies on the resume phi for the canonical induction being always available, which is why VPPhi are considered to have side-effects, to prevent their removal. This patch adds a new ResumeForEpilogue opcode to mark the resume phi as used for epilogue vectorization. This allows treating VPPhis in general as not having side-effects, enabling removal of unused VPPhis.
140 lines
6.6 KiB
LLVM
140 lines
6.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
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; RUN: opt -passes=loop-vectorize -mtriple=s390x -mcpu=z14 -S %s | FileCheck %s
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define void @test(ptr %p, i40 %a) {
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; CHECK-LABEL: define void @test(
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; CHECK-SAME: ptr [[P:%.*]], i40 [[A:%.*]]) #[[ATTR0:[0-9]+]] {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
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; CHECK: vector.ph:
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; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
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; CHECK: vector.body:
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; CHECK-NEXT: br i1 true, label [[PRED_STORE_IF:%.*]], label [[PRED_STORE_CONTINUE:%.*]]
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; CHECK: pred.store.if:
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; CHECK-NEXT: store i1 false, ptr [[P]], align 1
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; CHECK-NEXT: br label [[PRED_STORE_CONTINUE]]
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; CHECK: pred.store.continue:
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; CHECK-NEXT: br i1 true, label [[PRED_STORE_IF1:%.*]], label [[PRED_STORE_CONTINUE2:%.*]]
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; CHECK: pred.store.if1:
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; CHECK-NEXT: store i1 false, ptr [[P]], align 1
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; CHECK-NEXT: br label [[PRED_STORE_CONTINUE2]]
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; CHECK: pred.store.continue2:
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; CHECK-NEXT: br i1 true, label [[PRED_STORE_IF3:%.*]], label [[PRED_STORE_CONTINUE4:%.*]]
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; CHECK: pred.store.if3:
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; CHECK-NEXT: store i1 false, ptr [[P]], align 1
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; CHECK-NEXT: br label [[PRED_STORE_CONTINUE4]]
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; CHECK: pred.store.continue4:
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; CHECK-NEXT: br i1 true, label [[PRED_STORE_IF5:%.*]], label [[PRED_STORE_CONTINUE6:%.*]]
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; CHECK: pred.store.if5:
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; CHECK-NEXT: store i1 false, ptr [[P]], align 1
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; CHECK-NEXT: br label [[PRED_STORE_CONTINUE6]]
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; CHECK: pred.store.continue6:
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; CHECK-NEXT: br i1 true, label [[PRED_STORE_IF7:%.*]], label [[PRED_STORE_CONTINUE8:%.*]]
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; CHECK: pred.store.if7:
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; CHECK-NEXT: store i1 false, ptr [[P]], align 1
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; CHECK-NEXT: br label [[PRED_STORE_CONTINUE8]]
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; CHECK: pred.store.continue8:
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; CHECK-NEXT: br i1 true, label [[PRED_STORE_IF9:%.*]], label [[PRED_STORE_CONTINUE10:%.*]]
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; CHECK: pred.store.if9:
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; CHECK-NEXT: store i1 false, ptr [[P]], align 1
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; CHECK-NEXT: br label [[PRED_STORE_CONTINUE10]]
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; CHECK: pred.store.continue10:
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; CHECK-NEXT: br i1 true, label [[PRED_STORE_IF11:%.*]], label [[PRED_STORE_CONTINUE12:%.*]]
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; CHECK: pred.store.if11:
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; CHECK-NEXT: store i1 false, ptr [[P]], align 1
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; CHECK-NEXT: br label [[PRED_STORE_CONTINUE12]]
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; CHECK: pred.store.continue12:
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; CHECK-NEXT: br i1 true, label [[PRED_STORE_IF13:%.*]], label [[PRED_STORE_CONTINUE14:%.*]]
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; CHECK: pred.store.if13:
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; CHECK-NEXT: store i1 false, ptr [[P]], align 1
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; CHECK-NEXT: br label [[PRED_STORE_CONTINUE14]]
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; CHECK: pred.store.continue14:
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; CHECK-NEXT: br i1 true, label [[PRED_STORE_IF15:%.*]], label [[PRED_STORE_CONTINUE16:%.*]]
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; CHECK: pred.store.if15:
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; CHECK-NEXT: store i1 false, ptr [[P]], align 1
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; CHECK-NEXT: br label [[PRED_STORE_CONTINUE16]]
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; CHECK: pred.store.continue16:
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; CHECK-NEXT: br i1 true, label [[PRED_STORE_IF17:%.*]], label [[PRED_STORE_CONTINUE18:%.*]]
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; CHECK: pred.store.if17:
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; CHECK-NEXT: store i1 false, ptr [[P]], align 1
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; CHECK-NEXT: br label [[PRED_STORE_CONTINUE18]]
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; CHECK: pred.store.continue18:
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; CHECK-NEXT: br i1 false, label [[PRED_STORE_IF19:%.*]], label [[PRED_STORE_CONTINUE20:%.*]]
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; CHECK: pred.store.if19:
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; CHECK-NEXT: store i1 false, ptr [[P]], align 1
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; CHECK-NEXT: br label [[PRED_STORE_CONTINUE20]]
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; CHECK: pred.store.continue20:
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; CHECK-NEXT: br i1 false, label [[PRED_STORE_IF21:%.*]], label [[PRED_STORE_CONTINUE22:%.*]]
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; CHECK: pred.store.if21:
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; CHECK-NEXT: store i1 false, ptr [[P]], align 1
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; CHECK-NEXT: br label [[PRED_STORE_CONTINUE22]]
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; CHECK: pred.store.continue22:
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; CHECK-NEXT: br i1 false, label [[PRED_STORE_IF23:%.*]], label [[PRED_STORE_CONTINUE24:%.*]]
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; CHECK: pred.store.if23:
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; CHECK-NEXT: store i1 false, ptr [[P]], align 1
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; CHECK-NEXT: br label [[PRED_STORE_CONTINUE24]]
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; CHECK: pred.store.continue24:
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; CHECK-NEXT: br i1 false, label [[PRED_STORE_IF25:%.*]], label [[PRED_STORE_CONTINUE26:%.*]]
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; CHECK: pred.store.if25:
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; CHECK-NEXT: store i1 false, ptr [[P]], align 1
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; CHECK-NEXT: br label [[PRED_STORE_CONTINUE26]]
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; CHECK: pred.store.continue26:
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; CHECK-NEXT: br i1 false, label [[PRED_STORE_IF27:%.*]], label [[PRED_STORE_CONTINUE28:%.*]]
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; CHECK: pred.store.if27:
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; CHECK-NEXT: store i1 false, ptr [[P]], align 1
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; CHECK-NEXT: br label [[PRED_STORE_CONTINUE28]]
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; CHECK: pred.store.continue28:
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; CHECK-NEXT: br i1 false, label [[PRED_STORE_IF29:%.*]], label [[PRED_STORE_CONTINUE30:%.*]]
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; CHECK: pred.store.if29:
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; CHECK-NEXT: store i1 false, ptr [[P]], align 1
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; CHECK-NEXT: br label [[PRED_STORE_CONTINUE30]]
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; CHECK: pred.store.continue30:
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; CHECK-NEXT: br label [[MIDDLE_BLOCK:%.*]]
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; CHECK: middle.block:
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; CHECK-NEXT: br label [[EXIT:%.*]]
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; CHECK: scalar.ph:
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; CHECK-NEXT: br label [[FOR_BODY:%.*]]
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; CHECK: for.body:
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; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[FOR_BODY]] ]
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; CHECK-NEXT: [[SHL:%.*]] = shl i40 [[A]], 24
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; CHECK-NEXT: [[ASHR:%.*]] = ashr i40 [[SHL]], 28
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; CHECK-NEXT: [[TRUNC:%.*]] = trunc i40 [[ASHR]] to i32
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; CHECK-NEXT: [[ICMP_EQ:%.*]] = icmp eq i32 [[TRUNC]], 0
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; CHECK-NEXT: [[ZEXT:%.*]] = zext i1 [[ICMP_EQ]] to i32
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; CHECK-NEXT: [[ICMP_ULT:%.*]] = icmp ult i32 0, [[ZEXT]]
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; CHECK-NEXT: [[OR:%.*]] = or i1 [[ICMP_ULT]], true
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; CHECK-NEXT: [[ICMP_SGT:%.*]] = icmp sgt i1 [[OR]], false
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; CHECK-NEXT: store i1 [[ICMP_SGT]], ptr [[P]], align 1
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; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
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; CHECK-NEXT: [[COND:%.*]] = icmp ult i32 [[IV_NEXT]], 10
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; CHECK-NEXT: br i1 [[COND]], label [[FOR_BODY]], label [[EXIT]], !llvm.loop [[LOOP0:![0-9]+]]
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; CHECK: exit:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %for.body
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for.body: ; preds = %for.body, %entry
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%iv = phi i32 [ 0, %entry ], [ %iv.next, %for.body ]
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%shl = shl i40 %a, 24
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%ashr = ashr i40 %shl, 28
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%trunc = trunc i40 %ashr to i32
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%icmp.eq = icmp eq i32 %trunc, 0
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%zext = zext i1 %icmp.eq to i32
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%icmp.ult = icmp ult i32 0, %zext
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%or = or i1 %icmp.ult, true
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%icmp.sgt = icmp sgt i1 %or, false
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store i1 %icmp.sgt, ptr %p, align 1
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%iv.next = add i32 %iv, 1
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%cond = icmp ult i32 %iv.next, 10
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br i1 %cond, label %for.body, label %exit
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exit: ; preds = %for.body
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ret void
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}
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;.
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; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
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; CHECK: [[META1]] = !{!"llvm.loop.unroll.runtime.disable"}
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; CHECK: [[META2]] = !{!"llvm.loop.isvectorized", i32 1}
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;.
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