7d98b66e3d
This commit enables a pass in the backend which propagates the addrspace
of the pointers down to the last use, making sure the addrspace remains
consistent, and thus stripping any addrspacecast. This is required to
lower LLVM-IR to logical SPIR-V, which does not support generic
pointers.
This is now required as HLSL emits several address spaces, and thus
addrspacecasts in some cases:
Example 1: resource access
```llvm
%handle = tail call target("spirv.VulkanBuffer", ...)
%rptr = @llvm.spv.resource.getpointer(%handle, ...);
%cptr = addrspacecast ptr addrspace(11) %rptr to ptr
%fptr = load i32, ptr %cptr
```
Example 2: object methods
```llvm
define void @objectMethod(ptr %this) {
}
define void @foo(ptr addrspace(11) %object) {
call void @objectMethod(ptr addrspacecast(addrspace(11) %object to ptr));
}
```
288 lines
10 KiB
C++
288 lines
10 KiB
C++
//===- SPIRVTargetMachine.cpp - Define TargetMachine for SPIR-V -*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// Implements the info about SPIR-V target spec.
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//
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//===----------------------------------------------------------------------===//
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#include "SPIRVTargetMachine.h"
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#include "SPIRV.h"
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#include "SPIRVCallLowering.h"
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#include "SPIRVGlobalRegistry.h"
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#include "SPIRVLegalizerInfo.h"
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#include "SPIRVStructurizerWrapper.h"
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#include "SPIRVTargetObjectFile.h"
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#include "SPIRVTargetTransformInfo.h"
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#include "TargetInfo/SPIRVTargetInfo.h"
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#include "llvm/CodeGen/GlobalISel/IRTranslator.h"
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#include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
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#include "llvm/CodeGen/GlobalISel/Legalizer.h"
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#include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
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#include "llvm/CodeGen/TargetPassConfig.h"
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#include "llvm/InitializePasses.h"
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#include "llvm/MC/TargetRegistry.h"
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#include "llvm/Pass.h"
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#include "llvm/Passes/PassBuilder.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Transforms/Scalar.h"
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#include "llvm/Transforms/Scalar/Reg2Mem.h"
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#include "llvm/Transforms/Utils.h"
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#include <optional>
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using namespace llvm;
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extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSPIRVTarget() {
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// Register the target.
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RegisterTargetMachine<SPIRVTargetMachine> X(getTheSPIRV32Target());
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RegisterTargetMachine<SPIRVTargetMachine> Y(getTheSPIRV64Target());
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RegisterTargetMachine<SPIRVTargetMachine> Z(getTheSPIRVLogicalTarget());
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PassRegistry &PR = *PassRegistry::getPassRegistry();
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initializeGlobalISel(PR);
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initializeSPIRVModuleAnalysisPass(PR);
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initializeSPIRVAsmPrinterPass(PR);
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initializeSPIRVConvergenceRegionAnalysisWrapperPassPass(PR);
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initializeSPIRVStructurizerPass(PR);
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initializeSPIRVPreLegalizerCombinerPass(PR);
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initializeSPIRVLegalizePointerCastPass(PR);
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initializeSPIRVRegularizerPass(PR);
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initializeSPIRVPreLegalizerPass(PR);
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initializeSPIRVPostLegalizerPass(PR);
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initializeSPIRVMergeRegionExitTargetsPass(PR);
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initializeSPIRVEmitIntrinsicsPass(PR);
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initializeSPIRVEmitNonSemanticDIPass(PR);
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initializeSPIRVPrepareFunctionsPass(PR);
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initializeSPIRVStripConvergentIntrinsicsPass(PR);
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}
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static std::string computeDataLayout(const Triple &TT) {
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const auto Arch = TT.getArch();
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// TODO: this probably needs to be revisited:
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// Logical SPIR-V has no pointer size, so any fixed pointer size would be
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// wrong. The choice to default to 32 or 64 is just motivated by another
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// memory model used for graphics: PhysicalStorageBuffer64. But it shouldn't
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// mean anything.
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if (Arch == Triple::spirv32)
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return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-"
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"v256:256-v512:512-v1024:1024-n8:16:32:64-G1";
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if (Arch == Triple::spirv)
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return "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-"
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"v512:512-v1024:1024-n8:16:32:64-G10";
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if (TT.getVendor() == Triple::VendorType::AMD &&
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TT.getOS() == Triple::OSType::AMDHSA)
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return "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-"
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"v512:512-v1024:1024-n32:64-S32-G1-P4-A0";
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return "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-"
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"v512:512-v1024:1024-n8:16:32:64-G1";
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}
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static Reloc::Model getEffectiveRelocModel(std::optional<Reloc::Model> RM) {
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if (!RM)
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return Reloc::PIC_;
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return *RM;
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}
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// Pin SPIRVTargetObjectFile's vtables to this file.
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SPIRVTargetObjectFile::~SPIRVTargetObjectFile() {}
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SPIRVTargetMachine::SPIRVTargetMachine(const Target &T, const Triple &TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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std::optional<Reloc::Model> RM,
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std::optional<CodeModel::Model> CM,
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CodeGenOptLevel OL, bool JIT)
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: CodeGenTargetMachineImpl(T, computeDataLayout(TT), TT, CPU, FS, Options,
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getEffectiveRelocModel(RM),
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getEffectiveCodeModel(CM, CodeModel::Small), OL),
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TLOF(std::make_unique<SPIRVTargetObjectFile>()),
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Subtarget(TT, CPU.str(), FS.str(), *this) {
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initAsmInfo();
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setGlobalISel(true);
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setFastISel(false);
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setO0WantsFastISel(false);
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setRequiresStructuredCFG(false);
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}
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void SPIRVTargetMachine::registerPassBuilderCallbacks(PassBuilder &PB) {
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#define GET_PASS_REGISTRY "SPIRVPassRegistry.def"
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#include "llvm/Passes/TargetPassRegistry.inc"
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}
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namespace {
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// SPIR-V Code Generator Pass Configuration Options.
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class SPIRVPassConfig : public TargetPassConfig {
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public:
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SPIRVPassConfig(SPIRVTargetMachine &TM, PassManagerBase &PM)
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: TargetPassConfig(TM, PM), TM(TM) {}
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SPIRVTargetMachine &getSPIRVTargetMachine() const {
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return getTM<SPIRVTargetMachine>();
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}
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void addMachineSSAOptimization() override;
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void addIRPasses() override;
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void addISelPrepare() override;
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bool addIRTranslator() override;
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void addPreLegalizeMachineIR() override;
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bool addLegalizeMachineIR() override;
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bool addRegBankSelect() override;
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bool addGlobalInstructionSelect() override;
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FunctionPass *createTargetRegisterAllocator(bool) override;
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void addFastRegAlloc() override {}
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void addOptimizedRegAlloc() override {}
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void addPostRegAlloc() override;
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void addPreEmitPass() override;
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private:
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const SPIRVTargetMachine &TM;
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};
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} // namespace
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// We do not use physical registers, and maintain virtual registers throughout
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// the entire pipeline, so return nullptr to disable register allocation.
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FunctionPass *SPIRVPassConfig::createTargetRegisterAllocator(bool) {
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return nullptr;
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}
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// A place to disable passes that may break CFG.
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void SPIRVPassConfig::addMachineSSAOptimization() {
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TargetPassConfig::addMachineSSAOptimization();
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}
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// Disable passes that break from assuming no virtual registers exist.
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void SPIRVPassConfig::addPostRegAlloc() {
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// Do not work with vregs instead of physical regs.
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disablePass(&MachineCopyPropagationID);
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disablePass(&PostRAMachineSinkingID);
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disablePass(&PostRASchedulerID);
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disablePass(&FuncletLayoutID);
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disablePass(&StackMapLivenessID);
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disablePass(&PatchableFunctionID);
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disablePass(&ShrinkWrapID);
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disablePass(&LiveDebugValuesID);
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disablePass(&MachineLateInstrsCleanupID);
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disablePass(&RemoveLoadsIntoFakeUsesID);
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// Do not work with OpPhi.
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disablePass(&BranchFolderPassID);
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disablePass(&MachineBlockPlacementID);
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TargetPassConfig::addPostRegAlloc();
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}
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TargetTransformInfo
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SPIRVTargetMachine::getTargetTransformInfo(const Function &F) const {
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return TargetTransformInfo(std::make_unique<SPIRVTTIImpl>(this, F));
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}
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TargetPassConfig *SPIRVTargetMachine::createPassConfig(PassManagerBase &PM) {
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return new SPIRVPassConfig(*this, PM);
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}
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void SPIRVPassConfig::addIRPasses() {
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TargetPassConfig::addIRPasses();
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if (TM.getSubtargetImpl()->isVulkanEnv()) {
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// Vulkan does not allow address space casts. This pass is run to remove
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// address space casts that can be removed.
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// If an address space cast is not removed while targeting Vulkan, lowering
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// will fail during MIR lowering.
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addPass(createInferAddressSpacesPass());
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// 1. Simplify loop for subsequent transformations. After this steps, loops
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// have the following properties:
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// - loops have a single entry edge (pre-header to loop header).
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// - all loop exits are dominated by the loop pre-header.
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// - loops have a single back-edge.
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addPass(createLoopSimplifyPass());
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// 2. Removes registers whose lifetime spans across basic blocks. Also
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// removes phi nodes. This will greatly simplify the next steps.
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addPass(createRegToMemWrapperPass());
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// 3. Merge the convergence region exit nodes into one. After this step,
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// regions are single-entry, single-exit. This will help determine the
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// correct merge block.
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addPass(createSPIRVMergeRegionExitTargetsPass());
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// 4. Structurize.
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addPass(createSPIRVStructurizerPass());
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// 5. Reduce the amount of variables required by pushing some operations
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// back to virtual registers.
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addPass(createPromoteMemoryToRegisterPass());
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}
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addPass(createSPIRVRegularizerPass());
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addPass(createSPIRVPrepareFunctionsPass(TM));
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addPass(createSPIRVStripConvergenceIntrinsicsPass());
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}
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void SPIRVPassConfig::addISelPrepare() {
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addPass(createSPIRVEmitIntrinsicsPass(&getTM<SPIRVTargetMachine>()));
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if (TM.getSubtargetImpl()->isVulkanEnv())
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addPass(createSPIRVLegalizePointerCastPass(&getTM<SPIRVTargetMachine>()));
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TargetPassConfig::addISelPrepare();
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}
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bool SPIRVPassConfig::addIRTranslator() {
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addPass(new IRTranslator(getOptLevel()));
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return false;
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}
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void SPIRVPassConfig::addPreLegalizeMachineIR() {
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addPass(createSPIRVPreLegalizerCombiner());
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addPass(createSPIRVPreLegalizerPass());
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}
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// Use the default legalizer.
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bool SPIRVPassConfig::addLegalizeMachineIR() {
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addPass(new Legalizer());
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addPass(createSPIRVPostLegalizerPass());
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return false;
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}
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// Do not add the RegBankSelect pass, as we only ever need virtual registers.
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bool SPIRVPassConfig::addRegBankSelect() {
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disablePass(&RegBankSelect::ID);
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return false;
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}
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static cl::opt<bool> SPVEnableNonSemanticDI(
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"spv-emit-nonsemantic-debug-info",
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cl::desc("Emit SPIR-V NonSemantic.Shader.DebugInfo.100 instructions"),
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cl::Optional, cl::init(false));
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void SPIRVPassConfig::addPreEmitPass() {
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if (SPVEnableNonSemanticDI) {
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addPass(createSPIRVEmitNonSemanticDIPass(&getTM<SPIRVTargetMachine>()));
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}
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}
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namespace {
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// A custom subclass of InstructionSelect, which is mostly the same except from
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// not requiring RegBankSelect to occur previously.
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class SPIRVInstructionSelect : public InstructionSelect {
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// We don't use register banks, so unset the requirement for them
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MachineFunctionProperties getRequiredProperties() const override {
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return InstructionSelect::getRequiredProperties().reset(
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MachineFunctionProperties::Property::RegBankSelected);
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}
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};
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} // namespace
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// Add the custom SPIRVInstructionSelect from above.
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bool SPIRVPassConfig::addGlobalInstructionSelect() {
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addPass(new SPIRVInstructionSelect());
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return false;
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}
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