a1e1a84d2c
PTX 8.8+ introduces 256-bit-wide vector loads/stores under certain conditions. This change extends the backend to lower these loads/stores. It also overrides getLoadStoreVecRegBitWidth for NVPTX, allowing the LoadStoreVectorizer to create these wider vector operations. See the spec for the three relevant PTX instructions here: - https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-ld - https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-ld-global-nc - https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-st
This directory contains tests for the MIR file format parser and printer. It was necessary to split the tests across different targets as no single target covers all features available in machine IR. Tests for codegen passes should NOT be here but in test/CodeGen/sometarget. As a rule of thumb this directory should only contain tests using 'llc -run-pass none'.