c5afcfe0bb
If the broadcast is already the full vector width, try to prefer a blend/vshuff64x2 over a vector insertion which is usually lower latency (and sometimes a lower uop count), and reduces changes in vector sizes that can interfere with further combines. Updated version of #133083 - which lead to infinite loops due to shuffle lowering recreating the INSERT_SUBVECTOR pattern, this variant creates the BLENDI/SHUF128 nodes directly.
30 lines
1.8 KiB
LLVM
30 lines
1.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-- -mcpu=skx | FileCheck %s
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define void @insert_subvector_broadcast_as_blend() {
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; CHECK-LABEL: insert_subvector_broadcast_as_blend:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movq (%rax), %rax
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; CHECK-NEXT: incq %rax
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; CHECK-NEXT: vpbroadcastq %rax, %zmm0
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; CHECK-NEXT: vpslldq {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7]
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; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm1
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; CHECK-NEXT: vshuff64x2 {{.*#+}} zmm1 = zmm1[0,1,2,3],zmm0[4,5,6,7]
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; CHECK-NEXT: vpcmpltq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %k0
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; CHECK-NEXT: vpcmpltq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k1
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; CHECK-NEXT: kunpckbw %k0, %k1, %k1
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; CHECK-NEXT: vmovdqu8 {{.*#+}} xmm0 {%k1} {z} = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1]
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; CHECK-NEXT: vmovdqa %xmm0, (%rax)
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; CHECK-NEXT: vzeroupper
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; CHECK-NEXT: retq
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%load4 = load i64, ptr poison, align 32
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%add = add i64 %load4, 1
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%insertelement5 = insertelement <16 x i64> zeroinitializer, i64 %add, i64 1
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%shufflevector = shufflevector <16 x i64> %insertelement5, <16 x i64> poison, <16 x i32> <i32 0, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
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%icmp6 = icmp slt <16 x i64> %shufflevector, <i64 9223372036854775806, i64 2, i64 3, i64 4, i64 5, i64 6, i64 7, i64 8, i64 9, i64 10, i64 11, i64 12, i64 13, i64 14, i64 15, i64 16>
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%shufflevector7 = shufflevector <16 x i1> poison, <16 x i1> %icmp6, <16 x i32> <i32 0, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
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%zext = zext <16 x i1> %shufflevector7 to <16 x i8>
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store <16 x i8> %zext, ptr poison, align 32
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ret void
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}
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