62fd7f767c
tryLatency compares two sched candidates. For the top zone it prefers the one with lesser depth, but only if that depth is greater than the total latency of the instructions we've already scheduled -- otherwise its latency would be hidden and there would be no stall. Unfortunately it only tests the depth of one of the candidates. This can lead to situations where the TopDepthReduce heuristic does not kick in, but a lower priority heuristic chooses the other candidate, whose depth *is* greater than the already scheduled latency, which causes a stall. The fix is to apply the heuristic if the depth of *either* candidate is greater than the already scheduled latency. All this also applies to the BotHeightReduce heuristic in the bottom zone. Differential Revision: https://reviews.llvm.org/D72392
438 lines
15 KiB
LLVM
438 lines
15 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs \
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; RUN: -mtriple=powerpc64le-linux-gnu < %s | FileCheck \
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; RUN: -check-prefix=CHECK-LE %s
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; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs \
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; RUN: -mtriple=powerpc64le-linux-gnu -mcpu=pwr9 < %s | FileCheck \
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; RUN: -check-prefix=CHECK-P9-LE %s
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; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs \
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; RUN: -mtriple=powerpc64-linux-gnu < %s | FileCheck \
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; RUN: -check-prefix=CHECK-BE %s
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; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs \
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; RUN: -mtriple=powerpc-linux-gnu < %s | FileCheck \
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; RUN: -check-prefix=CHECK-32 %s
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define i32 @foo(i32 %n) local_unnamed_addr #0 "stack-probe-size"="32768" nounwind {
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; CHECK-LE-LABEL: foo:
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; CHECK-LE: # %bb.0:
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; CHECK-LE-NEXT: std r31, -8(r1)
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; CHECK-LE-NEXT: stdu r1, -48(r1)
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; CHECK-LE-NEXT: rldic r3, r3, 2, 30
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; CHECK-LE-NEXT: li r6, -32768
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; CHECK-LE-NEXT: mr r31, r1
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; CHECK-LE-NEXT: addi r3, r3, 15
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; CHECK-LE-NEXT: addi r4, r31, 48
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; CHECK-LE-NEXT: rldicl r3, r3, 60, 4
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; CHECK-LE-NEXT: rldicl r3, r3, 4, 29
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; CHECK-LE-NEXT: neg r5, r3
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; CHECK-LE-NEXT: divd r7, r5, r6
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; CHECK-LE-NEXT: add r3, r1, r5
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; CHECK-LE-NEXT: mulld r6, r7, r6
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; CHECK-LE-NEXT: sub r5, r5, r6
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; CHECK-LE-NEXT: stdux r4, r1, r5
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; CHECK-LE-NEXT: cmpd r1, r3
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; CHECK-LE-NEXT: beq cr0, .LBB0_2
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; CHECK-LE-NEXT: .LBB0_1:
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; CHECK-LE-NEXT: stdu r4, -32768(r1)
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; CHECK-LE-NEXT: cmpd r1, r3
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; CHECK-LE-NEXT: bne cr0, .LBB0_1
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; CHECK-LE-NEXT: .LBB0_2:
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; CHECK-LE-NEXT: li r4, 1
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; CHECK-LE-NEXT: addi r3, r1, 32
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; CHECK-LE-NEXT: stw r4, 4792(r3)
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; CHECK-LE-NEXT: lwz r3, 0(r3)
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; CHECK-LE-NEXT: ld r1, 0(r1)
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; CHECK-LE-NEXT: ld r31, -8(r1)
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; CHECK-LE-NEXT: blr
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;
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; CHECK-P9-LE-LABEL: foo:
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; CHECK-P9-LE: # %bb.0:
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; CHECK-P9-LE-NEXT: std r31, -8(r1)
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; CHECK-P9-LE-NEXT: stdu r1, -48(r1)
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; CHECK-P9-LE-NEXT: rldic r3, r3, 2, 30
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; CHECK-P9-LE-NEXT: addi r3, r3, 15
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; CHECK-P9-LE-NEXT: li r6, -32768
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; CHECK-P9-LE-NEXT: mr r31, r1
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; CHECK-P9-LE-NEXT: addi r4, r31, 48
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; CHECK-P9-LE-NEXT: rldicl r3, r3, 60, 4
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; CHECK-P9-LE-NEXT: rldicl r3, r3, 4, 29
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; CHECK-P9-LE-NEXT: neg r5, r3
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; CHECK-P9-LE-NEXT: divd r7, r5, r6
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; CHECK-P9-LE-NEXT: add r3, r1, r5
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; CHECK-P9-LE-NEXT: mulld r6, r7, r6
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; CHECK-P9-LE-NEXT: sub r5, r5, r6
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; CHECK-P9-LE-NEXT: stdux r4, r1, r5
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; CHECK-P9-LE-NEXT: cmpd r1, r3
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; CHECK-P9-LE-NEXT: beq cr0, .LBB0_2
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; CHECK-P9-LE-NEXT: .LBB0_1:
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; CHECK-P9-LE-NEXT: stdu r4, -32768(r1)
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; CHECK-P9-LE-NEXT: cmpd r1, r3
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; CHECK-P9-LE-NEXT: bne cr0, .LBB0_1
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; CHECK-P9-LE-NEXT: .LBB0_2:
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; CHECK-P9-LE-NEXT: li r4, 1
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; CHECK-P9-LE-NEXT: addi r3, r1, 32
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; CHECK-P9-LE-NEXT: stw r4, 4792(r3)
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; CHECK-P9-LE-NEXT: lwz r3, 0(r3)
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; CHECK-P9-LE-NEXT: ld r1, 0(r1)
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; CHECK-P9-LE-NEXT: ld r31, -8(r1)
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; CHECK-P9-LE-NEXT: blr
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;
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; CHECK-BE-LABEL: foo:
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; CHECK-BE: # %bb.0:
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; CHECK-BE-NEXT: std r31, -8(r1)
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; CHECK-BE-NEXT: stdu r1, -64(r1)
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; CHECK-BE-NEXT: rldic r3, r3, 2, 30
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; CHECK-BE-NEXT: li r6, -32768
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; CHECK-BE-NEXT: addi r3, r3, 15
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; CHECK-BE-NEXT: rldicl r3, r3, 60, 4
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; CHECK-BE-NEXT: mr r31, r1
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; CHECK-BE-NEXT: rldicl r3, r3, 4, 29
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; CHECK-BE-NEXT: addi r4, r31, 64
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; CHECK-BE-NEXT: neg r5, r3
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; CHECK-BE-NEXT: divd r7, r5, r6
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; CHECK-BE-NEXT: add r3, r1, r5
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; CHECK-BE-NEXT: mulld r6, r7, r6
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; CHECK-BE-NEXT: sub r5, r5, r6
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; CHECK-BE-NEXT: stdux r4, r1, r5
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; CHECK-BE-NEXT: cmpd r1, r3
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; CHECK-BE-NEXT: beq cr0, .LBB0_2
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; CHECK-BE-NEXT: .LBB0_1:
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; CHECK-BE-NEXT: stdu r4, -32768(r1)
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; CHECK-BE-NEXT: cmpd r1, r3
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; CHECK-BE-NEXT: bne cr0, .LBB0_1
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; CHECK-BE-NEXT: .LBB0_2:
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; CHECK-BE-NEXT: li r4, 1
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; CHECK-BE-NEXT: addi r3, r1, 48
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; CHECK-BE-NEXT: stw r4, 4792(r3)
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; CHECK-BE-NEXT: lwz r3, 0(r3)
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; CHECK-BE-NEXT: ld r1, 0(r1)
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; CHECK-BE-NEXT: ld r31, -8(r1)
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; CHECK-BE-NEXT: blr
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;
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; CHECK-32-LABEL: foo:
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; CHECK-32: # %bb.0:
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; CHECK-32-NEXT: stwu r1, -32(r1)
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; CHECK-32-NEXT: slwi r3, r3, 2
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; CHECK-32-NEXT: addi r3, r3, 15
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; CHECK-32-NEXT: rlwinm r3, r3, 0, 0, 27
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; CHECK-32-NEXT: neg r5, r3
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; CHECK-32-NEXT: li r6, -32768
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; CHECK-32-NEXT: divw r7, r5, r6
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; CHECK-32-NEXT: stw r31, 28(r1)
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; CHECK-32-NEXT: mr r31, r1
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; CHECK-32-NEXT: addi r4, r31, 32
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; CHECK-32-NEXT: add r3, r1, r5
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; CHECK-32-NEXT: mullw r6, r7, r6
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; CHECK-32-NEXT: sub r5, r5, r6
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; CHECK-32-NEXT: stwux r4, r1, r5
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; CHECK-32-NEXT: cmpw r1, r3
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; CHECK-32-NEXT: beq cr0, .LBB0_2
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; CHECK-32-NEXT: .LBB0_1:
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; CHECK-32-NEXT: stwu r4, -32768(r1)
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; CHECK-32-NEXT: cmpw r1, r3
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; CHECK-32-NEXT: bne cr0, .LBB0_1
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; CHECK-32-NEXT: .LBB0_2:
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; CHECK-32-NEXT: li r4, 1
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; CHECK-32-NEXT: addi r3, r1, 16
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; CHECK-32-NEXT: stw r4, 4792(r3)
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; CHECK-32-NEXT: lwz r3, 0(r3)
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; CHECK-32-NEXT: lwz r31, 0(r1)
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; CHECK-32-NEXT: lwz r0, -4(r31)
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; CHECK-32-NEXT: mr r1, r31
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; CHECK-32-NEXT: mr r31, r0
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; CHECK-32-NEXT: blr
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%a = alloca i32, i32 %n, align 16
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%b = getelementptr inbounds i32, i32* %a, i64 1198
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store volatile i32 1, i32* %b
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%c = load volatile i32, i32* %a
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ret i32 %c
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}
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define i32 @bar(i32 %n) local_unnamed_addr #0 nounwind {
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; CHECK-LE-LABEL: bar:
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; CHECK-LE: # %bb.0:
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; CHECK-LE-NEXT: std r31, -8(r1)
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; CHECK-LE-NEXT: stdu r1, -48(r1)
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; CHECK-LE-NEXT: rldic r4, r3, 2, 30
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; CHECK-LE-NEXT: li r7, -4096
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; CHECK-LE-NEXT: mr r31, r1
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; CHECK-LE-NEXT: addi r4, r4, 15
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; CHECK-LE-NEXT: addi r5, r31, 48
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; CHECK-LE-NEXT: rldicl r4, r4, 60, 4
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; CHECK-LE-NEXT: rldicl r4, r4, 4, 29
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; CHECK-LE-NEXT: neg r6, r4
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; CHECK-LE-NEXT: divd r8, r6, r7
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; CHECK-LE-NEXT: add r4, r1, r6
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; CHECK-LE-NEXT: mulld r7, r8, r7
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; CHECK-LE-NEXT: sub r6, r6, r7
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; CHECK-LE-NEXT: stdux r5, r1, r6
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; CHECK-LE-NEXT: cmpd r1, r4
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; CHECK-LE-NEXT: beq cr0, .LBB1_2
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; CHECK-LE-NEXT: .LBB1_1:
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; CHECK-LE-NEXT: stdu r5, -4096(r1)
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; CHECK-LE-NEXT: cmpd r1, r4
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; CHECK-LE-NEXT: bne cr0, .LBB1_1
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; CHECK-LE-NEXT: .LBB1_2:
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; CHECK-LE-NEXT: extsw r3, r3
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; CHECK-LE-NEXT: li r5, 1
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; CHECK-LE-NEXT: addi r4, r1, 32
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; CHECK-LE-NEXT: sldi r3, r3, 2
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; CHECK-LE-NEXT: add r3, r4, r3
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; CHECK-LE-NEXT: stw r5, 4096(r3)
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; CHECK-LE-NEXT: lwz r3, 0(r4)
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; CHECK-LE-NEXT: ld r1, 0(r1)
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; CHECK-LE-NEXT: ld r31, -8(r1)
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; CHECK-LE-NEXT: blr
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;
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; CHECK-P9-LE-LABEL: bar:
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; CHECK-P9-LE: # %bb.0:
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; CHECK-P9-LE-NEXT: std r31, -8(r1)
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; CHECK-P9-LE-NEXT: stdu r1, -48(r1)
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; CHECK-P9-LE-NEXT: rldic r4, r3, 2, 30
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; CHECK-P9-LE-NEXT: addi r4, r4, 15
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; CHECK-P9-LE-NEXT: li r7, -4096
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; CHECK-P9-LE-NEXT: mr r31, r1
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; CHECK-P9-LE-NEXT: addi r5, r31, 48
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; CHECK-P9-LE-NEXT: rldicl r4, r4, 60, 4
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; CHECK-P9-LE-NEXT: rldicl r4, r4, 4, 29
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; CHECK-P9-LE-NEXT: neg r6, r4
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; CHECK-P9-LE-NEXT: divd r8, r6, r7
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; CHECK-P9-LE-NEXT: add r4, r1, r6
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; CHECK-P9-LE-NEXT: mulld r7, r8, r7
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; CHECK-P9-LE-NEXT: sub r6, r6, r7
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; CHECK-P9-LE-NEXT: stdux r5, r1, r6
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; CHECK-P9-LE-NEXT: cmpd r1, r4
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; CHECK-P9-LE-NEXT: beq cr0, .LBB1_2
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; CHECK-P9-LE-NEXT: .LBB1_1:
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; CHECK-P9-LE-NEXT: stdu r5, -4096(r1)
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; CHECK-P9-LE-NEXT: cmpd r1, r4
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; CHECK-P9-LE-NEXT: bne cr0, .LBB1_1
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; CHECK-P9-LE-NEXT: .LBB1_2:
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; CHECK-P9-LE-NEXT: extswsli r3, r3, 2
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; CHECK-P9-LE-NEXT: li r5, 1
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; CHECK-P9-LE-NEXT: addi r4, r1, 32
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; CHECK-P9-LE-NEXT: add r3, r4, r3
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; CHECK-P9-LE-NEXT: stw r5, 4096(r3)
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; CHECK-P9-LE-NEXT: lwz r3, 0(r4)
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; CHECK-P9-LE-NEXT: ld r1, 0(r1)
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; CHECK-P9-LE-NEXT: ld r31, -8(r1)
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; CHECK-P9-LE-NEXT: blr
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;
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; CHECK-BE-LABEL: bar:
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; CHECK-BE: # %bb.0:
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; CHECK-BE-NEXT: std r31, -8(r1)
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; CHECK-BE-NEXT: stdu r1, -64(r1)
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; CHECK-BE-NEXT: rldic r4, r3, 2, 30
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; CHECK-BE-NEXT: li r7, -4096
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; CHECK-BE-NEXT: addi r4, r4, 15
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; CHECK-BE-NEXT: rldicl r4, r4, 60, 4
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; CHECK-BE-NEXT: mr r31, r1
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; CHECK-BE-NEXT: rldicl r4, r4, 4, 29
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; CHECK-BE-NEXT: addi r5, r31, 64
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; CHECK-BE-NEXT: neg r6, r4
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; CHECK-BE-NEXT: divd r8, r6, r7
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; CHECK-BE-NEXT: add r4, r1, r6
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; CHECK-BE-NEXT: mulld r7, r8, r7
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; CHECK-BE-NEXT: sub r6, r6, r7
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; CHECK-BE-NEXT: stdux r5, r1, r6
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; CHECK-BE-NEXT: cmpd r1, r4
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; CHECK-BE-NEXT: beq cr0, .LBB1_2
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; CHECK-BE-NEXT: .LBB1_1:
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; CHECK-BE-NEXT: stdu r5, -4096(r1)
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; CHECK-BE-NEXT: cmpd r1, r4
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; CHECK-BE-NEXT: bne cr0, .LBB1_1
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; CHECK-BE-NEXT: .LBB1_2:
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; CHECK-BE-NEXT: extsw r3, r3
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; CHECK-BE-NEXT: addi r4, r1, 48
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; CHECK-BE-NEXT: sldi r3, r3, 2
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; CHECK-BE-NEXT: li r5, 1
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; CHECK-BE-NEXT: add r3, r4, r3
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; CHECK-BE-NEXT: stw r5, 4096(r3)
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; CHECK-BE-NEXT: lwz r3, 0(r4)
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; CHECK-BE-NEXT: ld r1, 0(r1)
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; CHECK-BE-NEXT: ld r31, -8(r1)
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; CHECK-BE-NEXT: blr
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;
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; CHECK-32-LABEL: bar:
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; CHECK-32: # %bb.0:
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; CHECK-32-NEXT: stwu r1, -32(r1)
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; CHECK-32-NEXT: slwi r3, r3, 2
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; CHECK-32-NEXT: addi r4, r3, 15
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; CHECK-32-NEXT: rlwinm r4, r4, 0, 0, 27
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; CHECK-32-NEXT: neg r6, r4
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; CHECK-32-NEXT: li r7, -4096
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; CHECK-32-NEXT: divw r8, r6, r7
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; CHECK-32-NEXT: stw r31, 28(r1)
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; CHECK-32-NEXT: mr r31, r1
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; CHECK-32-NEXT: addi r5, r31, 32
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; CHECK-32-NEXT: add r4, r1, r6
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; CHECK-32-NEXT: mullw r7, r8, r7
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; CHECK-32-NEXT: sub r6, r6, r7
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; CHECK-32-NEXT: stwux r5, r1, r6
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; CHECK-32-NEXT: cmpw r1, r4
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; CHECK-32-NEXT: beq cr0, .LBB1_2
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; CHECK-32-NEXT: .LBB1_1:
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; CHECK-32-NEXT: stwu r5, -4096(r1)
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; CHECK-32-NEXT: cmpw r1, r4
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; CHECK-32-NEXT: bne cr0, .LBB1_1
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; CHECK-32-NEXT: .LBB1_2:
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; CHECK-32-NEXT: addi r4, r1, 16
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; CHECK-32-NEXT: li r5, 1
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; CHECK-32-NEXT: add r3, r4, r3
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; CHECK-32-NEXT: stw r5, 4096(r3)
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; CHECK-32-NEXT: lwz r3, 0(r4)
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; CHECK-32-NEXT: lwz r31, 0(r1)
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; CHECK-32-NEXT: lwz r0, -4(r31)
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; CHECK-32-NEXT: mr r1, r31
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; CHECK-32-NEXT: mr r31, r0
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; CHECK-32-NEXT: blr
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%a = alloca i32, i32 %n, align 16
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%i = add i32 %n, 1024
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%b = getelementptr inbounds i32, i32* %a, i32 %i
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store volatile i32 1, i32* %b
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%c = load volatile i32, i32* %a
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ret i32 %c
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}
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define i32 @f(i32 %n) local_unnamed_addr #0 "stack-probe-size"="65536" nounwind {
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; CHECK-LE-LABEL: f:
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; CHECK-LE: # %bb.0:
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; CHECK-LE-NEXT: std r31, -8(r1)
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; CHECK-LE-NEXT: stdu r1, -48(r1)
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; CHECK-LE-NEXT: rldic r3, r3, 2, 30
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; CHECK-LE-NEXT: lis r5, -1
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; CHECK-LE-NEXT: mr r31, r1
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; CHECK-LE-NEXT: addi r3, r3, 15
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; CHECK-LE-NEXT: ori r5, r5, 0
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; CHECK-LE-NEXT: addi r4, r31, 48
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; CHECK-LE-NEXT: rldicl r3, r3, 60, 4
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; CHECK-LE-NEXT: rldicl r3, r3, 4, 29
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; CHECK-LE-NEXT: neg r6, r3
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; CHECK-LE-NEXT: divd r7, r6, r5
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; CHECK-LE-NEXT: add r3, r1, r6
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; CHECK-LE-NEXT: mulld r7, r7, r5
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; CHECK-LE-NEXT: sub r6, r6, r7
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; CHECK-LE-NEXT: stdux r4, r1, r6
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; CHECK-LE-NEXT: cmpd r1, r3
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; CHECK-LE-NEXT: beq cr0, .LBB2_2
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; CHECK-LE-NEXT: .LBB2_1:
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; CHECK-LE-NEXT: stdux r4, r1, r5
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; CHECK-LE-NEXT: cmpd r1, r3
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; CHECK-LE-NEXT: bne cr0, .LBB2_1
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; CHECK-LE-NEXT: .LBB2_2:
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; CHECK-LE-NEXT: li r4, 1
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; CHECK-LE-NEXT: addi r3, r1, 32
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; CHECK-LE-NEXT: stw r4, 4792(r3)
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; CHECK-LE-NEXT: lwz r3, 0(r3)
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; CHECK-LE-NEXT: ld r1, 0(r1)
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; CHECK-LE-NEXT: ld r31, -8(r1)
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; CHECK-LE-NEXT: blr
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;
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; CHECK-P9-LE-LABEL: f:
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; CHECK-P9-LE: # %bb.0:
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; CHECK-P9-LE-NEXT: std r31, -8(r1)
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; CHECK-P9-LE-NEXT: stdu r1, -48(r1)
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; CHECK-P9-LE-NEXT: rldic r3, r3, 2, 30
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; CHECK-P9-LE-NEXT: addi r3, r3, 15
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; CHECK-P9-LE-NEXT: lis r5, -1
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; CHECK-P9-LE-NEXT: ori r5, r5, 0
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; CHECK-P9-LE-NEXT: mr r31, r1
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; CHECK-P9-LE-NEXT: addi r4, r31, 48
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; CHECK-P9-LE-NEXT: rldicl r3, r3, 60, 4
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; CHECK-P9-LE-NEXT: rldicl r3, r3, 4, 29
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; CHECK-P9-LE-NEXT: neg r6, r3
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; CHECK-P9-LE-NEXT: divd r7, r6, r5
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; CHECK-P9-LE-NEXT: add r3, r1, r6
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; CHECK-P9-LE-NEXT: mulld r7, r7, r5
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; CHECK-P9-LE-NEXT: sub r6, r6, r7
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; CHECK-P9-LE-NEXT: stdux r4, r1, r6
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; CHECK-P9-LE-NEXT: cmpd r1, r3
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; CHECK-P9-LE-NEXT: beq cr0, .LBB2_2
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; CHECK-P9-LE-NEXT: .LBB2_1:
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|
; CHECK-P9-LE-NEXT: stdux r4, r1, r5
|
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; CHECK-P9-LE-NEXT: cmpd r1, r3
|
|
; CHECK-P9-LE-NEXT: bne cr0, .LBB2_1
|
|
; CHECK-P9-LE-NEXT: .LBB2_2:
|
|
; CHECK-P9-LE-NEXT: li r4, 1
|
|
; CHECK-P9-LE-NEXT: addi r3, r1, 32
|
|
; CHECK-P9-LE-NEXT: stw r4, 4792(r3)
|
|
; CHECK-P9-LE-NEXT: lwz r3, 0(r3)
|
|
; CHECK-P9-LE-NEXT: ld r1, 0(r1)
|
|
; CHECK-P9-LE-NEXT: ld r31, -8(r1)
|
|
; CHECK-P9-LE-NEXT: blr
|
|
;
|
|
; CHECK-BE-LABEL: f:
|
|
; CHECK-BE: # %bb.0:
|
|
; CHECK-BE-NEXT: std r31, -8(r1)
|
|
; CHECK-BE-NEXT: stdu r1, -64(r1)
|
|
; CHECK-BE-NEXT: rldic r3, r3, 2, 30
|
|
; CHECK-BE-NEXT: lis r5, -1
|
|
; CHECK-BE-NEXT: addi r3, r3, 15
|
|
; CHECK-BE-NEXT: rldicl r3, r3, 60, 4
|
|
; CHECK-BE-NEXT: ori r5, r5, 0
|
|
; CHECK-BE-NEXT: rldicl r3, r3, 4, 29
|
|
; CHECK-BE-NEXT: mr r31, r1
|
|
; CHECK-BE-NEXT: neg r6, r3
|
|
; CHECK-BE-NEXT: divd r7, r6, r5
|
|
; CHECK-BE-NEXT: addi r4, r31, 64
|
|
; CHECK-BE-NEXT: mulld r7, r7, r5
|
|
; CHECK-BE-NEXT: add r3, r1, r6
|
|
; CHECK-BE-NEXT: sub r6, r6, r7
|
|
; CHECK-BE-NEXT: stdux r4, r1, r6
|
|
; CHECK-BE-NEXT: cmpd r1, r3
|
|
; CHECK-BE-NEXT: beq cr0, .LBB2_2
|
|
; CHECK-BE-NEXT: .LBB2_1:
|
|
; CHECK-BE-NEXT: stdux r4, r1, r5
|
|
; CHECK-BE-NEXT: cmpd r1, r3
|
|
; CHECK-BE-NEXT: bne cr0, .LBB2_1
|
|
; CHECK-BE-NEXT: .LBB2_2:
|
|
; CHECK-BE-NEXT: li r4, 1
|
|
; CHECK-BE-NEXT: addi r3, r1, 48
|
|
; CHECK-BE-NEXT: stw r4, 4792(r3)
|
|
; CHECK-BE-NEXT: lwz r3, 0(r3)
|
|
; CHECK-BE-NEXT: ld r1, 0(r1)
|
|
; CHECK-BE-NEXT: ld r31, -8(r1)
|
|
; CHECK-BE-NEXT: blr
|
|
;
|
|
; CHECK-32-LABEL: f:
|
|
; CHECK-32: # %bb.0:
|
|
; CHECK-32-NEXT: stwu r1, -32(r1)
|
|
; CHECK-32-NEXT: slwi r3, r3, 2
|
|
; CHECK-32-NEXT: addi r3, r3, 15
|
|
; CHECK-32-NEXT: rlwinm r3, r3, 0, 0, 27
|
|
; CHECK-32-NEXT: lis r5, -1
|
|
; CHECK-32-NEXT: neg r6, r3
|
|
; CHECK-32-NEXT: ori r5, r5, 0
|
|
; CHECK-32-NEXT: divw r7, r6, r5
|
|
; CHECK-32-NEXT: stw r31, 28(r1)
|
|
; CHECK-32-NEXT: mr r31, r1
|
|
; CHECK-32-NEXT: addi r4, r31, 32
|
|
; CHECK-32-NEXT: add r3, r1, r6
|
|
; CHECK-32-NEXT: mullw r7, r7, r5
|
|
; CHECK-32-NEXT: sub r6, r6, r7
|
|
; CHECK-32-NEXT: stwux r4, r1, r6
|
|
; CHECK-32-NEXT: cmpw r1, r3
|
|
; CHECK-32-NEXT: beq cr0, .LBB2_2
|
|
; CHECK-32-NEXT: .LBB2_1:
|
|
; CHECK-32-NEXT: stwux r4, r1, r5
|
|
; CHECK-32-NEXT: cmpw r1, r3
|
|
; CHECK-32-NEXT: bne cr0, .LBB2_1
|
|
; CHECK-32-NEXT: .LBB2_2:
|
|
; CHECK-32-NEXT: li r4, 1
|
|
; CHECK-32-NEXT: addi r3, r1, 16
|
|
; CHECK-32-NEXT: stw r4, 4792(r3)
|
|
; CHECK-32-NEXT: lwz r3, 0(r3)
|
|
; CHECK-32-NEXT: lwz r31, 0(r1)
|
|
; CHECK-32-NEXT: lwz r0, -4(r31)
|
|
; CHECK-32-NEXT: mr r1, r31
|
|
; CHECK-32-NEXT: mr r31, r0
|
|
; CHECK-32-NEXT: blr
|
|
%a = alloca i32, i32 %n, align 16
|
|
%b = getelementptr inbounds i32, i32* %a, i64 1198
|
|
store volatile i32 1, i32* %b
|
|
%c = load volatile i32, i32* %a
|
|
ret i32 %c
|
|
}
|
|
|
|
attributes #0 = {"probe-stack"="inline-asm"}
|