bee9664970
- Change InstrInfoEmitter to emit OpName as an enum class instead of an anonymous enum in the OpName namespace. - This will help clearly distinguish between values that are OpNames vs just operand indices and should help avoid bugs due to confusion between the two. - Rename OpName::OPERAND_LAST to NUM_OPERAND_NAMES. - Emit declaration of getOperandIdx() along with the OpName enum so it doesn't have to be repeated in various headers. - Also updated AMDGPU, RISCV, and WebAssembly backends to conform to the new definition of OpName (mostly mechanical changes).
60 lines
1.8 KiB
C++
60 lines
1.8 KiB
C++
//===-- AMDGPUMCTargetDesc.h - AMDGPU Target Descriptions -----*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// Provides AMDGPU specific target descriptions.
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//
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//===----------------------------------------------------------------------===//
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//
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#ifndef LLVM_LIB_TARGET_AMDGPU_MCTARGETDESC_AMDGPUMCTARGETDESC_H
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#define LLVM_LIB_TARGET_AMDGPU_MCTARGETDESC_AMDGPUMCTARGETDESC_H
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#include <cstdint>
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#include <memory>
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namespace llvm {
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class Target;
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class MCAsmBackend;
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class MCCodeEmitter;
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class MCContext;
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class MCInstrInfo;
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class MCObjectTargetWriter;
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class MCRegisterInfo;
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class MCSubtargetInfo;
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class MCTargetOptions;
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enum AMDGPUDwarfFlavour : unsigned { Wave64 = 0, Wave32 = 1 };
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MCRegisterInfo *createGCNMCRegisterInfo(AMDGPUDwarfFlavour DwarfFlavour);
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MCCodeEmitter *createAMDGPUMCCodeEmitter(const MCInstrInfo &MCII,
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MCContext &Ctx);
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MCAsmBackend *createAMDGPUAsmBackend(const Target &T,
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const MCSubtargetInfo &STI,
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const MCRegisterInfo &MRI,
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const MCTargetOptions &Options);
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std::unique_ptr<MCObjectTargetWriter>
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createAMDGPUELFObjectWriter(bool Is64Bit, uint8_t OSABI,
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bool HasRelocationAddend);
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} // namespace llvm
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#define GET_REGINFO_ENUM
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#include "AMDGPUGenRegisterInfo.inc"
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#define GET_INSTRINFO_ENUM
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#define GET_INSTRINFO_MC_HELPER_DECLS
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#include "AMDGPUGenInstrInfo.inc"
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#define GET_SUBTARGETINFO_ENUM
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#include "AMDGPUGenSubtargetInfo.inc"
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#endif
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