201208998f
These were using the virtual register encoding in Register which required including Register.h in MC layer code which is a layering violation. This also required converting Register with bit 31 set to MCRegister which should be an error. Register with bit 31 set should only be used for codegen virtual register. I'd like to add assertions to enforce this. Migrate to MCRegister and manually create an encoding with bit 31 set. WebAssembly also does this. We could consider adding interfaces to MCRegister for target specific virtual registers.
403 lines
14 KiB
C++
403 lines
14 KiB
C++
//===-- SPIRVInstPrinter.cpp - Output SPIR-V MCInsts as ASM -----*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This class prints a SPIR-V MCInst to a .s file.
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//
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//===----------------------------------------------------------------------===//
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#include "SPIRVInstPrinter.h"
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#include "SPIRV.h"
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#include "SPIRVBaseInfo.h"
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#include "llvm/ADT/APFloat.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCSymbol.h"
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#include "llvm/Support/Casting.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/FormattedStream.h"
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using namespace llvm;
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using namespace llvm::SPIRV;
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#define DEBUG_TYPE "asm-printer"
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// Include the auto-generated portion of the assembly writer.
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#include "SPIRVGenAsmWriter.inc"
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void SPIRVInstPrinter::printRemainingVariableOps(const MCInst *MI,
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unsigned StartIndex,
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raw_ostream &O,
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bool SkipFirstSpace,
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bool SkipImmediates) {
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const unsigned NumOps = MI->getNumOperands();
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for (unsigned i = StartIndex; i < NumOps; ++i) {
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if (!SkipImmediates || !MI->getOperand(i).isImm()) {
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if (!SkipFirstSpace || i != StartIndex)
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O << ' ';
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printOperand(MI, i, O);
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}
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}
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}
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void SPIRVInstPrinter::printOpConstantVarOps(const MCInst *MI,
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unsigned StartIndex,
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raw_ostream &O) {
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unsigned IsBitwidth16 = MI->getFlags() & SPIRV::INST_PRINTER_WIDTH16;
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const unsigned NumVarOps = MI->getNumOperands() - StartIndex;
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assert((NumVarOps == 1 || NumVarOps == 2) &&
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"Unsupported number of bits for literal variable");
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O << ' ';
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uint64_t Imm = MI->getOperand(StartIndex).getImm();
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// Handle 64 bit literals.
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if (NumVarOps == 2) {
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Imm |= (MI->getOperand(StartIndex + 1).getImm() << 32);
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}
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// Format and print float values.
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if (MI->getOpcode() == SPIRV::OpConstantF && IsBitwidth16 == 0) {
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APFloat FP = NumVarOps == 1 ? APFloat(APInt(32, Imm).bitsToFloat())
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: APFloat(APInt(64, Imm).bitsToDouble());
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// Print infinity and NaN as hex floats.
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// TODO: Make sure subnormal numbers are handled correctly as they may also
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// require hex float notation.
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if (FP.isInfinity()) {
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if (FP.isNegative())
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O << '-';
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O << "0x1p+128";
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return;
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}
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if (FP.isNaN()) {
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O << "0x1.8p+128";
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return;
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}
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// Format val as a decimal floating point or scientific notation (whichever
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// is shorter), with enough digits of precision to produce the exact value.
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O << format("%.*g", std::numeric_limits<double>::max_digits10,
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FP.convertToDouble());
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return;
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}
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// Print integer values directly.
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O << Imm;
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}
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void SPIRVInstPrinter::recordOpExtInstImport(const MCInst *MI) {
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MCRegister Reg = MI->getOperand(0).getReg();
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auto Name = getSPIRVStringOperand(*MI, 1);
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auto Set = getExtInstSetFromString(Name);
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ExtInstSetIDs.insert({Reg, Set});
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}
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void SPIRVInstPrinter::printInst(const MCInst *MI, uint64_t Address,
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StringRef Annot, const MCSubtargetInfo &STI,
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raw_ostream &OS) {
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const unsigned OpCode = MI->getOpcode();
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printInstruction(MI, Address, OS);
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if (OpCode == SPIRV::OpDecorate) {
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printOpDecorate(MI, OS);
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} else if (OpCode == SPIRV::OpExtInstImport) {
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recordOpExtInstImport(MI);
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} else if (OpCode == SPIRV::OpExtInst) {
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printOpExtInst(MI, OS);
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} else {
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// Print any extra operands for variadic instructions.
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const MCInstrDesc &MCDesc = MII.get(OpCode);
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if (MCDesc.isVariadic()) {
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const unsigned NumFixedOps = MCDesc.getNumOperands();
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const unsigned LastFixedIndex = NumFixedOps - 1;
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const int FirstVariableIndex = NumFixedOps;
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if (NumFixedOps > 0 && MCDesc.operands()[LastFixedIndex].OperandType ==
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MCOI::OPERAND_UNKNOWN) {
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// For instructions where a custom type (not reg or immediate) comes as
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// the last operand before the variable_ops. This is usually a StringImm
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// operand, but there are a few other cases.
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switch (OpCode) {
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case SPIRV::OpTypeImage:
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OS << ' ';
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printSymbolicOperand<OperandCategory::AccessQualifierOperand>(
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MI, FirstVariableIndex, OS);
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break;
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case SPIRV::OpVariable:
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OS << ' ';
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printOperand(MI, FirstVariableIndex, OS);
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break;
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case SPIRV::OpEntryPoint: {
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// Print the interface ID operands, skipping the name's string
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// literal.
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printRemainingVariableOps(MI, NumFixedOps, OS, false, true);
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break;
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}
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case SPIRV::OpExecutionMode:
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case SPIRV::OpExecutionModeId:
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case SPIRV::OpLoopMerge: {
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// Print any literals after the OPERAND_UNKNOWN argument normally.
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printRemainingVariableOps(MI, NumFixedOps, OS);
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break;
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}
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default:
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break; // printStringImm has already been handled.
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}
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} else {
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// For instructions with no fixed ops or a reg/immediate as the final
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// fixed operand, we can usually print the rest with "printOperand", but
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// check for a few cases with custom types first.
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switch (OpCode) {
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case SPIRV::OpLoad:
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case SPIRV::OpStore:
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OS << ' ';
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printSymbolicOperand<OperandCategory::MemoryOperandOperand>(
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MI, FirstVariableIndex, OS);
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printRemainingVariableOps(MI, FirstVariableIndex + 1, OS);
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break;
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case SPIRV::OpImageSampleImplicitLod:
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case SPIRV::OpImageSampleDrefImplicitLod:
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case SPIRV::OpImageSampleProjImplicitLod:
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case SPIRV::OpImageSampleProjDrefImplicitLod:
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case SPIRV::OpImageFetch:
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case SPIRV::OpImageGather:
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case SPIRV::OpImageDrefGather:
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case SPIRV::OpImageRead:
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case SPIRV::OpImageWrite:
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case SPIRV::OpImageSparseSampleImplicitLod:
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case SPIRV::OpImageSparseSampleDrefImplicitLod:
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case SPIRV::OpImageSparseSampleProjImplicitLod:
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case SPIRV::OpImageSparseSampleProjDrefImplicitLod:
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case SPIRV::OpImageSparseFetch:
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case SPIRV::OpImageSparseGather:
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case SPIRV::OpImageSparseDrefGather:
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case SPIRV::OpImageSparseRead:
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case SPIRV::OpImageSampleFootprintNV:
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OS << ' ';
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printSymbolicOperand<OperandCategory::ImageOperandOperand>(
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MI, FirstVariableIndex, OS);
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printRemainingVariableOps(MI, NumFixedOps + 1, OS);
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break;
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case SPIRV::OpCopyMemory:
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case SPIRV::OpCopyMemorySized: {
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const unsigned NumOps = MI->getNumOperands();
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for (unsigned i = NumFixedOps; i < NumOps; ++i) {
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OS << ' ';
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printSymbolicOperand<OperandCategory::MemoryOperandOperand>(MI, i,
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OS);
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if (MI->getOperand(i).getImm() & MemoryOperand::Aligned) {
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assert(i + 1 < NumOps && "Missing alignment operand");
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OS << ' ';
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printOperand(MI, i + 1, OS);
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i += 1;
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}
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}
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break;
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}
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case SPIRV::OpConstantI:
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case SPIRV::OpConstantF:
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// The last fixed operand along with any variadic operands that follow
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// are part of the variable value.
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printOpConstantVarOps(MI, NumFixedOps - 1, OS);
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break;
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case SPIRV::OpCooperativeMatrixMulAddKHR: {
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const unsigned NumOps = MI->getNumOperands();
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if (NumFixedOps == NumOps)
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break;
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OS << ' ';
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const unsigned MulAddOp = MI->getOperand(FirstVariableIndex).getImm();
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if (MulAddOp == 0) {
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printSymbolicOperand<
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OperandCategory::CooperativeMatrixOperandsOperand>(
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MI, FirstVariableIndex, OS);
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} else {
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std::string Buffer;
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for (unsigned Mask = 0x1;
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Mask != SPIRV::CooperativeMatrixOperands::
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MatrixResultBFloat16ComponentsINTEL;
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Mask <<= 1) {
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if (MulAddOp & Mask) {
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if (!Buffer.empty())
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Buffer += '|';
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Buffer += getSymbolicOperandMnemonic(
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OperandCategory::CooperativeMatrixOperandsOperand, Mask);
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}
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}
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OS << Buffer;
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}
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break;
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}
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default:
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printRemainingVariableOps(MI, NumFixedOps, OS);
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break;
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}
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}
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}
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}
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printAnnotation(OS, Annot);
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}
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void SPIRVInstPrinter::printOpExtInst(const MCInst *MI, raw_ostream &O) {
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// The fixed operands have already been printed, so just need to decide what
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// type of ExtInst operands to print based on the instruction set and number.
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const MCInstrDesc &MCDesc = MII.get(MI->getOpcode());
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unsigned NumFixedOps = MCDesc.getNumOperands();
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const auto NumOps = MI->getNumOperands();
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if (NumOps == NumFixedOps)
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return;
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O << ' ';
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// TODO: implement special printing for OpenCLExtInst::vstor*.
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printRemainingVariableOps(MI, NumFixedOps, O, true);
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}
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void SPIRVInstPrinter::printOpDecorate(const MCInst *MI, raw_ostream &O) {
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// The fixed operands have already been printed, so just need to decide what
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// type of decoration operands to print based on the Decoration type.
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const MCInstrDesc &MCDesc = MII.get(MI->getOpcode());
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unsigned NumFixedOps = MCDesc.getNumOperands();
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if (NumFixedOps != MI->getNumOperands()) {
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auto DecOp = MI->getOperand(NumFixedOps - 1);
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auto Dec = static_cast<Decoration::Decoration>(DecOp.getImm());
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O << ' ';
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switch (Dec) {
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case Decoration::BuiltIn:
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printSymbolicOperand<OperandCategory::BuiltInOperand>(MI, NumFixedOps, O);
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break;
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case Decoration::UniformId:
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printSymbolicOperand<OperandCategory::ScopeOperand>(MI, NumFixedOps, O);
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break;
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case Decoration::FuncParamAttr:
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printSymbolicOperand<OperandCategory::FunctionParameterAttributeOperand>(
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MI, NumFixedOps, O);
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break;
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case Decoration::FPRoundingMode:
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printSymbolicOperand<OperandCategory::FPRoundingModeOperand>(
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MI, NumFixedOps, O);
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break;
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case Decoration::FPFastMathMode:
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printSymbolicOperand<OperandCategory::FPFastMathModeOperand>(
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MI, NumFixedOps, O);
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break;
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case Decoration::LinkageAttributes:
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case Decoration::UserSemantic:
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printStringImm(MI, NumFixedOps, O);
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break;
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case Decoration::HostAccessINTEL:
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printOperand(MI, NumFixedOps, O);
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if (NumFixedOps + 1 < MI->getNumOperands()) {
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O << ' ';
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printStringImm(MI, NumFixedOps + 1, O);
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}
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break;
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default:
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printRemainingVariableOps(MI, NumFixedOps, O, true);
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break;
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}
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}
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}
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static void printExpr(const MCExpr *Expr, raw_ostream &O) {
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#ifndef NDEBUG
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const MCSymbolRefExpr *SRE;
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if (const MCBinaryExpr *BE = dyn_cast<MCBinaryExpr>(Expr))
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SRE = cast<MCSymbolRefExpr>(BE->getLHS());
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else
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SRE = cast<MCSymbolRefExpr>(Expr);
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MCSymbolRefExpr::VariantKind Kind = SRE->getKind();
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assert(Kind == MCSymbolRefExpr::VK_None);
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#endif
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O << *Expr;
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}
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void SPIRVInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O, const char *Modifier) {
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assert((Modifier == 0 || Modifier[0] == 0) && "No modifiers supported");
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if (OpNo < MI->getNumOperands()) {
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const MCOperand &Op = MI->getOperand(OpNo);
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if (Op.isReg())
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O << '%' << (getIDFromRegister(Op.getReg().id()) + 1);
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else if (Op.isImm())
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O << formatImm((int64_t)Op.getImm());
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else if (Op.isDFPImm())
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O << formatImm((double)Op.getDFPImm());
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else if (Op.isExpr())
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printExpr(Op.getExpr(), O);
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else
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llvm_unreachable("Unexpected operand type");
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}
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}
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void SPIRVInstPrinter::printStringImm(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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const unsigned NumOps = MI->getNumOperands();
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unsigned StrStartIndex = OpNo;
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while (StrStartIndex < NumOps) {
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if (MI->getOperand(StrStartIndex).isReg())
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break;
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std::string Str = getSPIRVStringOperand(*MI, StrStartIndex);
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if (StrStartIndex != OpNo)
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O << ' '; // Add a space if we're starting a new string/argument.
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O << '"';
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for (char c : Str) {
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// Escape ", \n characters (might break for complex UTF-8).
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if (c == '\n') {
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O.write("\\n", 2);
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} else {
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if (c == '"')
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O.write('\\');
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O.write(c);
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}
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}
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O << '"';
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unsigned numOpsInString = (Str.size() / 4) + 1;
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StrStartIndex += numOpsInString;
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// Check for final Op of "OpDecorate %x %stringImm %linkageAttribute".
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if (MI->getOpcode() == SPIRV::OpDecorate &&
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MI->getOperand(1).getImm() ==
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static_cast<unsigned>(Decoration::LinkageAttributes)) {
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O << ' ';
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printSymbolicOperand<OperandCategory::LinkageTypeOperand>(
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MI, StrStartIndex, O);
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break;
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}
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}
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}
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void SPIRVInstPrinter::printExtension(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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auto SetReg = MI->getOperand(2).getReg();
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auto Set = ExtInstSetIDs[SetReg];
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auto Op = MI->getOperand(OpNo).getImm();
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O << getExtInstName(Set, Op);
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}
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template <OperandCategory::OperandCategory category>
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void SPIRVInstPrinter::printSymbolicOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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if (OpNo < MI->getNumOperands()) {
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O << getSymbolicOperandMnemonic(category, MI->getOperand(OpNo).getImm());
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}
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}
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