d21b2e619a
The SPIR-V Backend uses the same set of utility functions, mostly though not entirely from SPIRVGlobalRegistry, to generate gMIR and SPIR-V opcodes, depending on the current stage of translation. This is controlled by an explicit EmitIR flag rather than the current translation pass, and there are legacy pieces of code where the EmitIR flag is declared so that it has a default true value, allowing using utility functions without explicitly declaring their intent to work either in gMIR or in SPIR-V part of the lowering process. While it may be ok to leave this default EmitIR flag as is in generation of scalar integer/float types, as we don't expect to see any dependent opcodes derived from such OpTypeXXX instructions, using of EmitIR by default in aggregation types is a source of hidden logical flaws and actual issues. This PR provides a partial fix to the problem by removing default status of EmitIR, requiring a user call site to explicitly announce its intent to generate gMIR or SPIR-V code, fixes several cases of misuse of EmitIR, and, the most important, fixes a nasty logical error that breaks passing of actually asked EmitIR value by the default value in the middle of the chain of calls, in the `findSPIRVType` call. The latter error was a source of issues in the post-instruction selection pass that has been getting gMIR code where SPIR-V was explicitly requested due to overloaded with default parameters internal API in SPIRVGlobalRegistry (most notably, `findSPIRVType`).
418 lines
16 KiB
C++
418 lines
16 KiB
C++
//===- SPIRVLegalizerInfo.cpp --- SPIR-V Legalization Rules ------*- C++ -*-==//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the targeting of the Machinelegalizer class for SPIR-V.
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//
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//===----------------------------------------------------------------------===//
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#include "SPIRVLegalizerInfo.h"
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#include "SPIRV.h"
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#include "SPIRVGlobalRegistry.h"
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#include "SPIRVSubtarget.h"
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#include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
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#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/TargetOpcodes.h"
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using namespace llvm;
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using namespace llvm::LegalizeActions;
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using namespace llvm::LegalityPredicates;
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// clang-format off
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static const std::set<unsigned> TypeFoldingSupportingOpcs = {
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TargetOpcode::G_ADD,
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TargetOpcode::G_FADD,
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TargetOpcode::G_STRICT_FADD,
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TargetOpcode::G_SUB,
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TargetOpcode::G_FSUB,
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TargetOpcode::G_STRICT_FSUB,
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TargetOpcode::G_MUL,
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TargetOpcode::G_FMUL,
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TargetOpcode::G_STRICT_FMUL,
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TargetOpcode::G_SDIV,
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TargetOpcode::G_UDIV,
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TargetOpcode::G_FDIV,
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TargetOpcode::G_STRICT_FDIV,
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TargetOpcode::G_SREM,
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TargetOpcode::G_UREM,
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TargetOpcode::G_FREM,
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TargetOpcode::G_STRICT_FREM,
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TargetOpcode::G_FNEG,
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TargetOpcode::G_CONSTANT,
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TargetOpcode::G_FCONSTANT,
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TargetOpcode::G_AND,
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TargetOpcode::G_OR,
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TargetOpcode::G_XOR,
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TargetOpcode::G_SHL,
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TargetOpcode::G_ASHR,
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TargetOpcode::G_LSHR,
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TargetOpcode::G_SELECT,
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TargetOpcode::G_EXTRACT_VECTOR_ELT,
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};
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// clang-format on
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bool isTypeFoldingSupported(unsigned Opcode) {
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return TypeFoldingSupportingOpcs.count(Opcode) > 0;
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}
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LegalityPredicate typeOfExtendedScalars(unsigned TypeIdx, bool IsExtendedInts) {
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return [IsExtendedInts, TypeIdx](const LegalityQuery &Query) {
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const LLT Ty = Query.Types[TypeIdx];
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return IsExtendedInts && Ty.isValid() && Ty.isScalar();
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};
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}
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SPIRVLegalizerInfo::SPIRVLegalizerInfo(const SPIRVSubtarget &ST) {
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using namespace TargetOpcode;
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this->ST = &ST;
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GR = ST.getSPIRVGlobalRegistry();
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const LLT s1 = LLT::scalar(1);
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const LLT s8 = LLT::scalar(8);
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const LLT s16 = LLT::scalar(16);
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const LLT s32 = LLT::scalar(32);
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const LLT s64 = LLT::scalar(64);
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const LLT v16s64 = LLT::fixed_vector(16, 64);
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const LLT v16s32 = LLT::fixed_vector(16, 32);
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const LLT v16s16 = LLT::fixed_vector(16, 16);
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const LLT v16s8 = LLT::fixed_vector(16, 8);
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const LLT v16s1 = LLT::fixed_vector(16, 1);
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const LLT v8s64 = LLT::fixed_vector(8, 64);
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const LLT v8s32 = LLT::fixed_vector(8, 32);
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const LLT v8s16 = LLT::fixed_vector(8, 16);
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const LLT v8s8 = LLT::fixed_vector(8, 8);
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const LLT v8s1 = LLT::fixed_vector(8, 1);
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const LLT v4s64 = LLT::fixed_vector(4, 64);
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const LLT v4s32 = LLT::fixed_vector(4, 32);
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const LLT v4s16 = LLT::fixed_vector(4, 16);
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const LLT v4s8 = LLT::fixed_vector(4, 8);
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const LLT v4s1 = LLT::fixed_vector(4, 1);
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const LLT v3s64 = LLT::fixed_vector(3, 64);
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const LLT v3s32 = LLT::fixed_vector(3, 32);
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const LLT v3s16 = LLT::fixed_vector(3, 16);
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const LLT v3s8 = LLT::fixed_vector(3, 8);
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const LLT v3s1 = LLT::fixed_vector(3, 1);
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const LLT v2s64 = LLT::fixed_vector(2, 64);
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const LLT v2s32 = LLT::fixed_vector(2, 32);
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const LLT v2s16 = LLT::fixed_vector(2, 16);
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const LLT v2s8 = LLT::fixed_vector(2, 8);
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const LLT v2s1 = LLT::fixed_vector(2, 1);
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const unsigned PSize = ST.getPointerSize();
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const LLT p0 = LLT::pointer(0, PSize); // Function
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const LLT p1 = LLT::pointer(1, PSize); // CrossWorkgroup
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const LLT p2 = LLT::pointer(2, PSize); // UniformConstant
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const LLT p3 = LLT::pointer(3, PSize); // Workgroup
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const LLT p4 = LLT::pointer(4, PSize); // Generic
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const LLT p5 =
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LLT::pointer(5, PSize); // Input, SPV_INTEL_usm_storage_classes (Device)
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const LLT p6 = LLT::pointer(6, PSize); // SPV_INTEL_usm_storage_classes (Host)
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const LLT p7 = LLT::pointer(7, PSize); // Input
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const LLT p8 = LLT::pointer(8, PSize); // Output
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const LLT p10 = LLT::pointer(10, PSize); // Private
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// TODO: remove copy-pasting here by using concatenation in some way.
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auto allPtrsScalarsAndVectors = {
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p0, p1, p2, p3, p4, p5, p6, p7, p8, p10,
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s1, s8, s16, s32, s64, v2s1, v2s8, v2s16, v2s32, v2s64,
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v3s1, v3s8, v3s16, v3s32, v3s64, v4s1, v4s8, v4s16, v4s32, v4s64,
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v8s1, v8s8, v8s16, v8s32, v8s64, v16s1, v16s8, v16s16, v16s32, v16s64};
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auto allVectors = {v2s1, v2s8, v2s16, v2s32, v2s64, v3s1, v3s8,
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v3s16, v3s32, v3s64, v4s1, v4s8, v4s16, v4s32,
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v4s64, v8s1, v8s8, v8s16, v8s32, v8s64, v16s1,
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v16s8, v16s16, v16s32, v16s64};
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auto allScalarsAndVectors = {
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s1, s8, s16, s32, s64, v2s1, v2s8, v2s16, v2s32, v2s64,
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v3s1, v3s8, v3s16, v3s32, v3s64, v4s1, v4s8, v4s16, v4s32, v4s64,
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v8s1, v8s8, v8s16, v8s32, v8s64, v16s1, v16s8, v16s16, v16s32, v16s64};
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auto allIntScalarsAndVectors = {s8, s16, s32, s64, v2s8, v2s16,
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v2s32, v2s64, v3s8, v3s16, v3s32, v3s64,
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v4s8, v4s16, v4s32, v4s64, v8s8, v8s16,
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v8s32, v8s64, v16s8, v16s16, v16s32, v16s64};
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auto allBoolScalarsAndVectors = {s1, v2s1, v3s1, v4s1, v8s1, v16s1};
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auto allIntScalars = {s8, s16, s32, s64};
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auto allFloatScalars = {s16, s32, s64};
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auto allFloatScalarsAndVectors = {
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s16, s32, s64, v2s16, v2s32, v2s64, v3s16, v3s32, v3s64,
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v4s16, v4s32, v4s64, v8s16, v8s32, v8s64, v16s16, v16s32, v16s64};
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auto allFloatAndIntScalarsAndPtrs = {s8, s16, s32, s64, p0, p1, p2,
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p3, p4, p5, p6, p7, p8, p10};
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auto allPtrs = {p0, p1, p2, p3, p4, p5, p6, p7, p8, p10};
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bool IsExtendedInts =
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ST.canUseExtension(
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SPIRV::Extension::SPV_INTEL_arbitrary_precision_integers) ||
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ST.canUseExtension(SPIRV::Extension::SPV_KHR_bit_instructions);
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auto extendedScalarsAndVectors =
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[IsExtendedInts](const LegalityQuery &Query) {
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const LLT Ty = Query.Types[0];
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return IsExtendedInts && Ty.isValid() && !Ty.isPointerOrPointerVector();
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};
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auto extendedScalarsAndVectorsProduct = [IsExtendedInts](
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const LegalityQuery &Query) {
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const LLT Ty1 = Query.Types[0], Ty2 = Query.Types[1];
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return IsExtendedInts && Ty1.isValid() && Ty2.isValid() &&
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!Ty1.isPointerOrPointerVector() && !Ty2.isPointerOrPointerVector();
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};
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auto extendedPtrsScalarsAndVectors =
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[IsExtendedInts](const LegalityQuery &Query) {
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const LLT Ty = Query.Types[0];
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return IsExtendedInts && Ty.isValid();
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};
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for (auto Opc : TypeFoldingSupportingOpcs)
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getActionDefinitionsBuilder(Opc).custom();
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getActionDefinitionsBuilder(G_GLOBAL_VALUE).alwaysLegal();
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// TODO: add proper rules for vectors legalization.
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getActionDefinitionsBuilder(
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{G_BUILD_VECTOR, G_SHUFFLE_VECTOR, G_SPLAT_VECTOR})
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.alwaysLegal();
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// Vector Reduction Operations
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getActionDefinitionsBuilder(
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{G_VECREDUCE_SMIN, G_VECREDUCE_SMAX, G_VECREDUCE_UMIN, G_VECREDUCE_UMAX,
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G_VECREDUCE_ADD, G_VECREDUCE_MUL, G_VECREDUCE_FMUL, G_VECREDUCE_FMIN,
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G_VECREDUCE_FMAX, G_VECREDUCE_FMINIMUM, G_VECREDUCE_FMAXIMUM,
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G_VECREDUCE_OR, G_VECREDUCE_AND, G_VECREDUCE_XOR})
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.legalFor(allVectors)
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.scalarize(1)
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.lower();
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getActionDefinitionsBuilder({G_VECREDUCE_SEQ_FADD, G_VECREDUCE_SEQ_FMUL})
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.scalarize(2)
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.lower();
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// Merge/Unmerge
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// TODO: add proper legalization rules.
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getActionDefinitionsBuilder(G_UNMERGE_VALUES).alwaysLegal();
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getActionDefinitionsBuilder({G_MEMCPY, G_MEMMOVE})
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.legalIf(all(typeInSet(0, allPtrs), typeInSet(1, allPtrs)));
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getActionDefinitionsBuilder(G_MEMSET).legalIf(
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all(typeInSet(0, allPtrs), typeInSet(1, allIntScalars)));
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getActionDefinitionsBuilder(G_ADDRSPACE_CAST)
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.legalForCartesianProduct(allPtrs, allPtrs);
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getActionDefinitionsBuilder({G_LOAD, G_STORE}).legalIf(typeInSet(1, allPtrs));
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getActionDefinitionsBuilder({G_SMIN, G_SMAX, G_UMIN, G_UMAX, G_ABS,
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G_BITREVERSE, G_SADDSAT, G_UADDSAT, G_SSUBSAT,
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G_USUBSAT, G_SCMP, G_UCMP})
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.legalFor(allIntScalarsAndVectors)
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.legalIf(extendedScalarsAndVectors);
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getActionDefinitionsBuilder({G_FMA, G_STRICT_FMA})
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.legalFor(allFloatScalarsAndVectors);
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getActionDefinitionsBuilder(G_STRICT_FLDEXP)
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.legalForCartesianProduct(allFloatScalarsAndVectors, allIntScalars);
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getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI})
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.legalForCartesianProduct(allIntScalarsAndVectors,
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allFloatScalarsAndVectors);
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getActionDefinitionsBuilder({G_SITOFP, G_UITOFP})
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.legalForCartesianProduct(allFloatScalarsAndVectors,
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allScalarsAndVectors);
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getActionDefinitionsBuilder(G_CTPOP)
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.legalForCartesianProduct(allIntScalarsAndVectors)
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.legalIf(extendedScalarsAndVectorsProduct);
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// Extensions.
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getActionDefinitionsBuilder({G_TRUNC, G_ZEXT, G_SEXT, G_ANYEXT})
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.legalForCartesianProduct(allScalarsAndVectors)
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.legalIf(extendedScalarsAndVectorsProduct);
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getActionDefinitionsBuilder(G_PHI)
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.legalFor(allPtrsScalarsAndVectors)
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.legalIf(extendedPtrsScalarsAndVectors);
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getActionDefinitionsBuilder(G_BITCAST).legalIf(
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all(typeInSet(0, allPtrsScalarsAndVectors),
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typeInSet(1, allPtrsScalarsAndVectors)));
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getActionDefinitionsBuilder({G_IMPLICIT_DEF, G_FREEZE}).alwaysLegal();
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getActionDefinitionsBuilder({G_STACKSAVE, G_STACKRESTORE}).alwaysLegal();
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getActionDefinitionsBuilder(G_INTTOPTR)
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.legalForCartesianProduct(allPtrs, allIntScalars)
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.legalIf(
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all(typeInSet(0, allPtrs), typeOfExtendedScalars(1, IsExtendedInts)));
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getActionDefinitionsBuilder(G_PTRTOINT)
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.legalForCartesianProduct(allIntScalars, allPtrs)
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.legalIf(
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all(typeOfExtendedScalars(0, IsExtendedInts), typeInSet(1, allPtrs)));
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getActionDefinitionsBuilder(G_PTR_ADD)
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.legalForCartesianProduct(allPtrs, allIntScalars)
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.legalIf(
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all(typeInSet(0, allPtrs), typeOfExtendedScalars(1, IsExtendedInts)));
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// ST.canDirectlyComparePointers() for pointer args is supported in
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// legalizeCustom().
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getActionDefinitionsBuilder(G_ICMP).customIf(
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all(typeInSet(0, allBoolScalarsAndVectors),
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typeInSet(1, allPtrsScalarsAndVectors)));
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getActionDefinitionsBuilder(G_FCMP).legalIf(
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all(typeInSet(0, allBoolScalarsAndVectors),
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typeInSet(1, allFloatScalarsAndVectors)));
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getActionDefinitionsBuilder({G_ATOMICRMW_OR, G_ATOMICRMW_ADD, G_ATOMICRMW_AND,
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G_ATOMICRMW_MAX, G_ATOMICRMW_MIN,
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G_ATOMICRMW_SUB, G_ATOMICRMW_XOR,
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G_ATOMICRMW_UMAX, G_ATOMICRMW_UMIN})
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.legalForCartesianProduct(allIntScalars, allPtrs);
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getActionDefinitionsBuilder(
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{G_ATOMICRMW_FADD, G_ATOMICRMW_FSUB, G_ATOMICRMW_FMIN, G_ATOMICRMW_FMAX})
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.legalForCartesianProduct(allFloatScalars, allPtrs);
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getActionDefinitionsBuilder(G_ATOMICRMW_XCHG)
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.legalForCartesianProduct(allFloatAndIntScalarsAndPtrs, allPtrs);
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getActionDefinitionsBuilder(G_ATOMIC_CMPXCHG_WITH_SUCCESS).lower();
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// TODO: add proper legalization rules.
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getActionDefinitionsBuilder(G_ATOMIC_CMPXCHG).alwaysLegal();
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getActionDefinitionsBuilder(
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{G_UADDO, G_SADDO, G_USUBO, G_SSUBO, G_UMULO, G_SMULO})
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.alwaysLegal();
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// FP conversions.
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getActionDefinitionsBuilder({G_FPTRUNC, G_FPEXT})
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.legalForCartesianProduct(allFloatScalarsAndVectors);
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// Pointer-handling.
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getActionDefinitionsBuilder(G_FRAME_INDEX).legalFor({p0});
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// Control-flow. In some cases (e.g. constants) s1 may be promoted to s32.
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getActionDefinitionsBuilder(G_BRCOND).legalFor({s1, s32});
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// TODO: Review the target OpenCL and GLSL Extended Instruction Set specs to
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// tighten these requirements. Many of these math functions are only legal on
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// specific bitwidths, so they are not selectable for
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// allFloatScalarsAndVectors.
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getActionDefinitionsBuilder({G_STRICT_FSQRT,
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G_FPOW,
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G_FEXP,
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G_FEXP2,
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G_FLOG,
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G_FLOG2,
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G_FLOG10,
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G_FABS,
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G_FMINNUM,
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G_FMAXNUM,
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G_FCEIL,
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G_FCOS,
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G_FSIN,
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G_FTAN,
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G_FACOS,
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G_FASIN,
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G_FATAN,
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G_FATAN2,
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G_FCOSH,
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G_FSINH,
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G_FTANH,
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G_FSQRT,
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G_FFLOOR,
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G_FRINT,
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G_FNEARBYINT,
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G_INTRINSIC_ROUND,
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G_INTRINSIC_TRUNC,
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G_FMINIMUM,
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G_FMAXIMUM,
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G_INTRINSIC_ROUNDEVEN})
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.legalFor(allFloatScalarsAndVectors);
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getActionDefinitionsBuilder(G_FCOPYSIGN)
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.legalForCartesianProduct(allFloatScalarsAndVectors,
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allFloatScalarsAndVectors);
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getActionDefinitionsBuilder(G_FPOWI).legalForCartesianProduct(
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allFloatScalarsAndVectors, allIntScalarsAndVectors);
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if (ST.canUseExtInstSet(SPIRV::InstructionSet::OpenCL_std)) {
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getActionDefinitionsBuilder(
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{G_CTTZ, G_CTTZ_ZERO_UNDEF, G_CTLZ, G_CTLZ_ZERO_UNDEF})
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.legalForCartesianProduct(allIntScalarsAndVectors,
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allIntScalarsAndVectors);
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// Struct return types become a single scalar, so cannot easily legalize.
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getActionDefinitionsBuilder({G_SMULH, G_UMULH}).alwaysLegal();
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}
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getLegacyLegalizerInfo().computeTables();
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verify(*ST.getInstrInfo());
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}
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static Register convertPtrToInt(Register Reg, LLT ConvTy, SPIRVType *SpvType,
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LegalizerHelper &Helper,
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MachineRegisterInfo &MRI,
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SPIRVGlobalRegistry *GR) {
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Register ConvReg = MRI.createGenericVirtualRegister(ConvTy);
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MRI.setRegClass(ConvReg, GR->getRegClass(SpvType));
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GR->assignSPIRVTypeToVReg(SpvType, ConvReg, Helper.MIRBuilder.getMF());
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Helper.MIRBuilder.buildInstr(TargetOpcode::G_PTRTOINT)
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.addDef(ConvReg)
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.addUse(Reg);
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return ConvReg;
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}
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|
|
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bool SPIRVLegalizerInfo::legalizeCustom(
|
|
LegalizerHelper &Helper, MachineInstr &MI,
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|
LostDebugLocObserver &LocObserver) const {
|
|
auto Opc = MI.getOpcode();
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|
MachineRegisterInfo &MRI = MI.getMF()->getRegInfo();
|
|
if (!isTypeFoldingSupported(Opc)) {
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|
assert(Opc == TargetOpcode::G_ICMP);
|
|
assert(GR->getSPIRVTypeForVReg(MI.getOperand(0).getReg()));
|
|
auto &Op0 = MI.getOperand(2);
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|
auto &Op1 = MI.getOperand(3);
|
|
Register Reg0 = Op0.getReg();
|
|
Register Reg1 = Op1.getReg();
|
|
CmpInst::Predicate Cond =
|
|
static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate());
|
|
if ((!ST->canDirectlyComparePointers() ||
|
|
(Cond != CmpInst::ICMP_EQ && Cond != CmpInst::ICMP_NE)) &&
|
|
MRI.getType(Reg0).isPointer() && MRI.getType(Reg1).isPointer()) {
|
|
LLT ConvT = LLT::scalar(ST->getPointerSize());
|
|
Type *LLVMTy = IntegerType::get(MI.getMF()->getFunction().getContext(),
|
|
ST->getPointerSize());
|
|
SPIRVType *SpirvTy = GR->getOrCreateSPIRVType(
|
|
LLVMTy, Helper.MIRBuilder, SPIRV::AccessQualifier::ReadWrite, true);
|
|
Op0.setReg(convertPtrToInt(Reg0, ConvT, SpirvTy, Helper, MRI, GR));
|
|
Op1.setReg(convertPtrToInt(Reg1, ConvT, SpirvTy, Helper, MRI, GR));
|
|
}
|
|
return true;
|
|
}
|
|
// TODO: implement legalization for other opcodes.
|
|
return true;
|
|
}
|