a216358ce7
This performs the minimal replacment of amdgpu-no-agpr to amdgpu-agpr-alloc=0. Most of the test diffs are due to the new attribute sorting later alphabetically. We could do better by trying to perform range merging in the attributor, and trying to pick non-0 values.
348 lines
14 KiB
LLVM
348 lines
14 KiB
LLVM
; RUN: llc -mtriple=amdgcn-- -mcpu=tahiti -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
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; TODO: Test with flat scratch
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; GCN-LABEL: {{^}}store_fi_lifetime:
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; GCN: v_mov_b32_e32 [[FI:v[0-9]+]], 0{{$}}
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; GCN: buffer_store_dword [[FI]]
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define amdgpu_kernel void @store_fi_lifetime(ptr addrspace(1) %out, i32 %in) #0 {
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entry:
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%b = alloca i8, addrspace(5)
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call void @llvm.lifetime.start.p5(i64 1, ptr addrspace(5) %b)
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store volatile ptr addrspace(5) %b, ptr addrspace(1) undef
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call void @llvm.lifetime.end.p5(i64 1, ptr addrspace(5) %b)
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ret void
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}
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; GCN-LABEL: {{^}}stored_fi_to_lds:
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; GCN: s_load_dword [[LDSPTR:s[0-9]+]]
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; GCN: v_mov_b32_e32 [[ZERO0:v[0-9]+]], 0{{$}}
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; GCN: buffer_store_dword v{{[0-9]+}}, off,
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; GCN: v_mov_b32_e32 [[VLDSPTR:v[0-9]+]], [[LDSPTR]]
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; GCN: ds_write_b32 [[VLDSPTR]], [[ZERO0]]
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define amdgpu_kernel void @stored_fi_to_lds(ptr addrspace(3) %ptr) #0 {
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%tmp = alloca float, addrspace(5)
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store float 4.0, ptr addrspace(5) %tmp
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store ptr addrspace(5) %tmp, ptr addrspace(3) %ptr
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ret void
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}
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; Offset is applied
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; GCN-LABEL: {{^}}stored_fi_to_lds_2_small_objects:
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; GCN-DAG: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0{{$}}
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; GCN-DAG: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}}
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; GCN-DAG: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:4{{$}}
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; GCN-DAG: s_load_dword [[LDSPTR:s[0-9]+]]
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; GCN-DAG: v_mov_b32_e32 [[VLDSPTR:v[0-9]+]], [[LDSPTR]]
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; GCN: ds_write_b32 [[VLDSPTR]], [[ZERO]]
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; GCN-DAG: v_mov_b32_e32 [[FI1:v[0-9]+]], 4{{$}}
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; GCN: ds_write_b32 [[VLDSPTR]], [[FI1]]
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define amdgpu_kernel void @stored_fi_to_lds_2_small_objects(ptr addrspace(3) %ptr) #0 {
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%tmp0 = alloca float, addrspace(5)
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%tmp1 = alloca float, addrspace(5)
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store float 4.0, ptr addrspace(5) %tmp0
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store float 4.0, ptr addrspace(5) %tmp1
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store volatile ptr addrspace(5) %tmp0, ptr addrspace(3) %ptr
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store volatile ptr addrspace(5) %tmp1, ptr addrspace(3) %ptr
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ret void
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}
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; Same frame index is used multiple times in the store
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; GCN-LABEL: {{^}}stored_fi_to_self:
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; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0x4d2{{$}}
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; GCN: buffer_store_dword [[K]], off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}}
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; GCN-DAG: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0{{$}}
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; GCN: buffer_store_dword [[ZERO]], off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}}
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define amdgpu_kernel void @stored_fi_to_self() #0 {
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%tmp = alloca ptr addrspace(5), addrspace(5)
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; Avoid optimizing everything out
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store volatile ptr addrspace(5) inttoptr (i32 1234 to ptr addrspace(5)), ptr addrspace(5) %tmp
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store volatile ptr addrspace(5) %tmp, ptr addrspace(5) %tmp
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ret void
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}
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; GCN-LABEL: {{^}}stored_fi_to_self_offset:
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; GCN-DAG: v_mov_b32_e32 [[K0:v[0-9]+]], 32{{$}}
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; GCN: buffer_store_dword [[K0]], off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}}
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; GCN-DAG: v_mov_b32_e32 [[K1:v[0-9]+]], 0x4d2{{$}}
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; GCN: buffer_store_dword [[K1]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:2048{{$}}
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; GCN: v_mov_b32_e32 [[OFFSETK:v[0-9]+]], 0x800{{$}}
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; GCN: buffer_store_dword [[OFFSETK]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:2048{{$}}
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define amdgpu_kernel void @stored_fi_to_self_offset() #0 {
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%tmp0 = alloca [512 x i32], addrspace(5)
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%tmp1 = alloca ptr addrspace(5), addrspace(5)
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; Avoid optimizing everything out
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store volatile i32 32, ptr addrspace(5) %tmp0
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store volatile ptr addrspace(5) inttoptr (i32 1234 to ptr addrspace(5)), ptr addrspace(5) %tmp1
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store volatile ptr addrspace(5) %tmp1, ptr addrspace(5) %tmp1
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ret void
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}
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; GCN-LABEL: {{^}}stored_fi_to_fi:
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; GCN: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}}
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; GCN: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:4{{$}}
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; GCN: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:8{{$}}
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; GCN: v_mov_b32_e32 [[FI1:v[0-9]+]], 4{{$}}
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; GCN: buffer_store_dword [[FI1]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:8{{$}}
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; GCN: v_mov_b32_e32 [[FI2:v[0-9]+]], 8{{$}}
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; GCN: buffer_store_dword [[FI2]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:4{{$}}
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define amdgpu_kernel void @stored_fi_to_fi() #0 {
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%tmp0 = alloca ptr addrspace(5), addrspace(5)
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%tmp1 = alloca ptr addrspace(5), addrspace(5)
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%tmp2 = alloca ptr addrspace(5), addrspace(5)
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store volatile ptr addrspace(5) inttoptr (i32 1234 to ptr addrspace(5)), ptr addrspace(5) %tmp0
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store volatile ptr addrspace(5) inttoptr (i32 5678 to ptr addrspace(5)), ptr addrspace(5) %tmp1
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store volatile ptr addrspace(5) inttoptr (i32 9999 to ptr addrspace(5)), ptr addrspace(5) %tmp2
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store volatile ptr addrspace(5) %tmp1, ptr addrspace(5) %tmp2 ; store offset 0 at offset 4
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store volatile ptr addrspace(5) %tmp2, ptr addrspace(5) %tmp1 ; store offset 4 at offset 0
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ret void
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}
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; GCN-LABEL: {{^}}stored_fi_to_global:
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; GCN: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}}
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; GCN: v_mov_b32_e32 [[FI:v[0-9]+]], 0{{$}}
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; GCN: buffer_store_dword [[FI]]
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define amdgpu_kernel void @stored_fi_to_global(ptr addrspace(1) %ptr) #0 {
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%tmp = alloca float, addrspace(5)
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store float 0.0, ptr addrspace(5) %tmp
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store ptr addrspace(5) %tmp, ptr addrspace(1) %ptr
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ret void
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}
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; Offset is applied
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; GCN-LABEL: {{^}}stored_fi_to_global_2_small_objects:
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; GCN: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}}
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; GCN: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:4{{$}}
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; GCN: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:8{{$}}
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; GCN: v_mov_b32_e32 [[FI1:v[0-9]+]], 4{{$}}
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; GCN: buffer_store_dword [[FI1]], off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}}
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; GCN-DAG: v_mov_b32_e32 [[FI2:v[0-9]+]], 8{{$}}
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; GCN: buffer_store_dword [[FI2]], off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}}
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define amdgpu_kernel void @stored_fi_to_global_2_small_objects(ptr addrspace(1) %ptr) #0 {
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%tmp0 = alloca float, addrspace(5)
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%tmp1 = alloca float, addrspace(5)
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%tmp2 = alloca float, addrspace(5)
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store volatile float 0.0, ptr addrspace(5) %tmp0
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store volatile float 0.0, ptr addrspace(5) %tmp1
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store volatile float 0.0, ptr addrspace(5) %tmp2
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store volatile ptr addrspace(5) %tmp1, ptr addrspace(1) %ptr
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store volatile ptr addrspace(5) %tmp2, ptr addrspace(1) %ptr
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ret void
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}
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; GCN-LABEL: {{^}}kernel_stored_fi_to_global_huge_frame_offset:
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; GCN: v_mov_b32_e32 [[BASE_0:v[0-9]+]], 0{{$}}
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; GCN: buffer_store_dword [[BASE_0]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:4{{$}}
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; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0x3e7{{$}}
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; GCN-DAG: v_mov_b32_e32 [[V_BASE_1_OFF:v[0-9]+]], 0x4000{{$}}
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; GCN: buffer_store_dword [[K]], [[V_BASE_1_OFF]], s{{\[[0-9]+:[0-9]+\]}}, 0 offen{{$}}
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; GCN: buffer_store_dword [[V_BASE_1_OFF]], off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}}
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define amdgpu_kernel void @kernel_stored_fi_to_global_huge_frame_offset(ptr addrspace(1) %ptr) #0 {
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%tmp0 = alloca [4096 x i32], addrspace(5)
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%tmp1 = alloca [4096 x i32], addrspace(5)
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store volatile i32 0, ptr addrspace(5) %tmp0
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%gep1.tmp0 = getelementptr [4096 x i32], ptr addrspace(5) %tmp0, i32 0, i32 4095
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store volatile i32 999, ptr addrspace(5) %gep1.tmp0
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%gep0.tmp1 = getelementptr [4096 x i32], ptr addrspace(5) %tmp0, i32 0, i32 14
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store ptr addrspace(5) %gep0.tmp1, ptr addrspace(1) %ptr
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ret void
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}
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; FIXME: Shift of SP repeated twice
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; GCN-LABEL: {{^}}func_stored_fi_to_global_huge_frame_offset:
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; GCN-DAG: v_lshr_b32_e64 [[FI_TMP_0:v[0-9]+]], s32, 6
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; GCN-DAG: v_mov_b32_e32 [[BASE_0:v[0-9]+]], 0{{$}}
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; GCN: buffer_store_dword [[BASE_0]], off, s{{\[[0-9]+:[0-9]+\]}}, s32 offset:4{{$}}
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; GCN-DAG: v_add_i32_e32 [[FI_0:v[0-9]+]], vcc, 0x4000, [[FI_TMP_0]]{{$}}
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; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0x3e7{{$}}
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; GCN: buffer_store_dword [[K]], [[FI_0]], s{{\[[0-9]+:[0-9]+\]}}, 0 offen{{$}}
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; GCN: v_lshr_b32_e64 [[FI_TMP_1:v[0-9]+]], s32, 6
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; GCN: v_add_i32_e32 [[BASE_0_1:v[0-9]+]], vcc, 60, [[FI_TMP_1]]{{$}}
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; GCN: buffer_store_dword [[BASE_0_1]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64
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define void @func_stored_fi_to_global_huge_frame_offset(ptr addrspace(1) %ptr) #0 {
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%tmp0 = alloca [4096 x i32], addrspace(5)
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%tmp1 = alloca [4096 x i32], addrspace(5)
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store volatile i32 0, ptr addrspace(5) %tmp0
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%gep1.tmp0 = getelementptr [4096 x i32], ptr addrspace(5) %tmp0, i32 0, i32 4095
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store volatile i32 999, ptr addrspace(5) %gep1.tmp0
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%gep0.tmp1 = getelementptr [4096 x i32], ptr addrspace(5) %tmp0, i32 0, i32 14
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store ptr addrspace(5) %gep0.tmp1, ptr addrspace(1) %ptr
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ret void
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}
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@g1 = external addrspace(1) global ptr addrspace(5)
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; This was leaving a dead node around resulting in failing to select
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; on the leftover AssertZext's ValueType operand.
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; GCN-LABEL: {{^}}cannot_select_assertzext_valuetype:
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; GCN: s_getpc_b64 s[[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]]
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; GCN: s_add_u32 s{{[0-9]+}}, s[[PC_LO]], g1@gotpcrel32@lo+4
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; GCN: s_addc_u32 s{{[0-9]+}}, s[[PC_HI]], g1@gotpcrel32@hi+12
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; GCN: v_mov_b32_e32 [[FI:v[0-9]+]], 0{{$}}
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; GCN: buffer_store_dword [[FI]]
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define amdgpu_kernel void @cannot_select_assertzext_valuetype(ptr addrspace(1) %out, i32 %idx) #0 {
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entry:
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%b = alloca i32, align 4, addrspace(5)
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%tmp1 = load volatile ptr addrspace(5), ptr addrspace(1) @g1, align 4
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%arrayidx = getelementptr inbounds i32, ptr addrspace(5) %tmp1, i32 %idx
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%tmp2 = load i32, ptr addrspace(5) %arrayidx, align 4
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store volatile ptr addrspace(5) %b, ptr addrspace(1) undef
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ret void
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}
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; GCN-LABEL: {{^}}func_alloca_offset0__use_asm_sgpr:
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; GCN: s_lshr_b32 [[FI:s[0-9]+]], s32, 6
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; GCN-NOT: [[FI]]
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; GCN: ; use [[FI]]
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define void @func_alloca_offset0__use_asm_sgpr() {
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%alloca = alloca i32, addrspace(5)
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call void asm sideeffect "; use $0", "s"(ptr addrspace(5) %alloca)
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ret void
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}
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; GCN-LABEL: {{^}}func_alloca_offset0__use_asm_vgpr:
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; GCN: v_lshr_b32_e64 [[FI:v[0-9]+]], s32, 6
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; GCN-NEXT: ;;#ASMSTART
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; GCN-NEXT: ; use [[FI]]
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define void @func_alloca_offset0__use_asm_vgpr() {
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%alloca = alloca i32, addrspace(5)
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call void asm sideeffect "; use $0", "v"(ptr addrspace(5) %alloca)
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ret void
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}
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; GCN-LABEL: {{^}}func_alloca_offset0__use_asm_phys_sgpr:
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; GCN: s_lshr_b32 [[FI:s[0-9]+]], s32, 6
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; GCN-NEXT: ;;#ASMSTART
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; GCN-NEXT: ; use [[FI]]
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define void @func_alloca_offset0__use_asm_phys_sgpr() {
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%alloca = alloca i32, addrspace(5)
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call void asm sideeffect "; use $0", "{s8}"(ptr addrspace(5) %alloca)
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ret void
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}
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; GCN-LABEL: {{^}}func_alloca_offset0__use_asm_phys_vgpr:
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; GCN: v_lshr_b32_e64 v8, s32, 6
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; GCN-NEXT: ;;#ASMSTART
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; GCN-NEXT: ; use v8
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define void @func_alloca_offset0__use_asm_phys_vgpr() {
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%alloca = alloca i32, addrspace(5)
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call void asm sideeffect "; use $0", "{v8}"(ptr addrspace(5) %alloca)
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ret void
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}
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; GCN-LABEL: {{^}}func_alloca_offset_use_asm_sgpr:
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; GCN: s_lshr_b32 [[FI0_TMP0:s[0-9]+]], s32, 6
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; GCN-NEXT: s_add_i32 [[FI0:s[0-9]+]], [[FI0_TMP0]], 16
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; GCN: s_lshr_b32 [[TMP:s[0-9]+]], s32, 6
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; GCN-NEXT: s_addk_i32 [[TMP]], 0x4010
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; GCN-NEXT: ;;#ASMSTART
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; GCN: ; use [[TMP]]
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define void @func_alloca_offset_use_asm_sgpr() {
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%alloca0 = alloca [4096 x i32], align 16, addrspace(5)
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%alloca1 = alloca i32, addrspace(5)
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call void asm sideeffect "; use $0", "s"(ptr addrspace(5) %alloca0)
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call void asm sideeffect "; use $0", "s"(ptr addrspace(5) %alloca1)
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ret void
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}
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; GCN-LABEL: {{^}}func_alloca_offset_use_asm_vgpr:
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; GCN: s_lshr_b32 [[S_FI:s[0-9]+]], s32, 6
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; GCN: v_lshr_b32_e64 [[V_FI:v[0-9]+]], s32, 6
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; GCN: s_movk_i32 vcc_lo, 0x4010
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; GCN: s_add_i32 [[S_FI]], [[S_FI]], 16
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; GCN-NEXT: ;;#ASMSTART
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; GCN-NEXT: ; use [[S_FI]]
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; GCN-NEXT: ;;#ASMEND
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; GCN-NEXT: v_add_i32_e32 [[V_FI:v[0-9]+]], vcc, vcc_lo, [[V_FI]]
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; GCN-NEXT: ;;#ASMSTART
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; GCN-NEXT: ; use [[V_FI]]
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; GCN-NEXT: ;;#ASMEND
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define void @func_alloca_offset_use_asm_vgpr() {
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%alloca0 = alloca [4096 x i32], align 16, addrspace(5)
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%alloca1 = alloca i32, addrspace(5)
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call void asm sideeffect "; use $0", "s"(ptr addrspace(5) %alloca0)
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call void asm sideeffect "; use $0", "v"(ptr addrspace(5) %alloca1)
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ret void
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}
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; GCN-LABEL: {{^}}kernel_alloca_offset_use_asm_sgpr:
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; GCN: s_mov_b32 [[FI0:s[0-9]+]], 16
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; GCN-NOT: v0
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; GCN: ;;#ASMSTART
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; GCN-NEXT: ; use [[FI0]]
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; GCN-NEXT: ;;#ASMEND
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; GCN: s_movk_i32 [[FI1:s[0-9]+]], 0x4010
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; GCN-NEXT: ;;#ASMSTART
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; GCN-NEXT: ; use [[FI1]]
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; GCN-NEXT: ;;#ASMEND
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define amdgpu_kernel void @kernel_alloca_offset_use_asm_sgpr() {
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%alloca0 = alloca [4096 x i32], align 16, addrspace(5)
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%alloca1 = alloca i32, addrspace(5)
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call void asm sideeffect "; use $0", "s"(ptr addrspace(5) %alloca0)
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call void asm sideeffect "; use $0", "s"(ptr addrspace(5) %alloca1)
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ret void
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}
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; GCN-LABEL: {{^}}kernel_alloca_offset_use_asm_vgpr:
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; GCN: v_mov_b32_e32 v0, 16
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; GCN-NOT: v0
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; GCN: ;;#ASMSTART
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; GCN-NEXT: ; use v0
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; GCN-NEXT: ;;#ASMEND
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; GCN: v_mov_b32_e32 v0, 0x4010
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; GCN-NEXT: ;;#ASMSTART
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; GCN-NEXT: ; use v0
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; GCN-NEXT: ;;#ASMEND
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define amdgpu_kernel void @kernel_alloca_offset_use_asm_vgpr() {
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%alloca0 = alloca [4096 x i32], align 16, addrspace(5)
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%alloca1 = alloca i32, addrspace(5)
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call void asm sideeffect "; use $0", "v"(ptr addrspace(5) %alloca0)
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call void asm sideeffect "; use $0", "v"(ptr addrspace(5) %alloca1)
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ret void
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}
|
|
|
|
; GCN-LABEL: {{^}}live_out_physreg_copy_add_fi:
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|
; GCN: s_or_b32 [[FI:s[0-9]+]], s{{[0-9]+}}, 4
|
|
; GCN: v_mov_b32_e32 v0, [[FI]]
|
|
; GCN: v_mov_b32_e32 v1
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|
; GCN: s_swappc_b64
|
|
define void @live_out_physreg_copy_add_fi(ptr %fptr) #2 {
|
|
bb:
|
|
%alloca = alloca [4 x i32], align 16, addrspace(5)
|
|
%addrspacecast = addrspacecast ptr addrspace(5) %alloca to ptr
|
|
%getelementptr = getelementptr i8, ptr %addrspacecast, i64 4
|
|
call void %fptr(ptr %getelementptr) #2
|
|
ret void
|
|
}
|
|
|
|
declare void @llvm.lifetime.start.p5(i64, ptr addrspace(5) nocapture) #1
|
|
declare void @llvm.lifetime.end.p5(i64, ptr addrspace(5) nocapture) #1
|
|
|
|
attributes #0 = { nounwind }
|
|
attributes #1 = { argmemonly nounwind }
|
|
attributes #2 = { "amdgpu-agpr-alloc"="0" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" }
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