a33a84ee63
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test gfx940 and gfx941 are no longer supported. This is one of a series of PRs to remove them from the code base. This PR uses gfx942 instead of gfx940 and gfx941 in the test RUN-lines (unless there is already a RUN-line for gfx942). The only notable difference in the test output is that gfx942 does not force the use of sc0 and sc1 on stores while gfx940 and gfx941 do (cf. https://reviews.llvm.org/D149986). For SWDEV-512631
97 lines
4.5 KiB
LLVM
97 lines
4.5 KiB
LLVM
; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GCN,DPP64,GFX90A
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; RUN: llc -mtriple=amdgcn -mcpu=gfx942 -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GCN,DPP64,DPPMOV64,GFX942
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GCN,DPP32,GFX10PLUS
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GCN,DPP32,GFX10PLUS
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; GCN-LABEL: {{^}}dpp64_ceil:
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; GCN: global_load_{{dwordx2|b64}} [[V:v\[[0-9:]+\]]],
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; DPP64: v_ceil_f64_dpp [[V]], [[V]] row_newbcast:1 row_mask:0xf bank_mask:0xf bound_ctrl:1{{$}}
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; DPP32-COUNT-2: v_mov_b32_dpp v{{[0-9]+}}, v{{[0-9]+}} row_share:1 row_mask:0xf bank_mask:0xf bound_ctrl:1{{$}}
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define amdgpu_kernel void @dpp64_ceil(ptr addrspace(1) %arg, i64 %in1) {
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%id = tail call i32 @llvm.amdgcn.workitem.id.x()
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%gep = getelementptr inbounds i64, ptr addrspace(1) %arg, i32 %id
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%load = load i64, ptr addrspace(1) %gep
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%tmp0 = call i64 @llvm.amdgcn.update.dpp.i64(i64 %in1, i64 %load, i32 337, i32 15, i32 15, i1 1) #0
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%tmp1 = bitcast i64 %tmp0 to double
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%round = tail call double @llvm.ceil.f64(double %tmp1)
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%tmp2 = bitcast double %round to i64
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store i64 %tmp2, ptr addrspace(1) %gep
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ret void
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}
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; GCN-LABEL: {{^}}dpp64_rcp:
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; GCN: global_load_{{dwordx2|b64}} [[V:v\[[0-9:]+\]]],
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; DPP64: v_rcp_f64_dpp [[V]], [[V]] row_newbcast:1 row_mask:0xf bank_mask:0xf bound_ctrl:1{{$}}
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; DPP32-COUNT-2: v_mov_b32_dpp v{{[0-9]+}}, v{{[0-9]+}} row_share:1 row_mask:0xf bank_mask:0xf bound_ctrl:1{{$}}
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define amdgpu_kernel void @dpp64_rcp(ptr addrspace(1) %arg, i64 %in1) {
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%id = tail call i32 @llvm.amdgcn.workitem.id.x()
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%gep = getelementptr inbounds i64, ptr addrspace(1) %arg, i32 %id
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%load = load i64, ptr addrspace(1) %gep
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%tmp0 = call i64 @llvm.amdgcn.update.dpp.i64(i64 %in1, i64 %load, i32 337, i32 15, i32 15, i1 1) #0
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%tmp1 = bitcast i64 %tmp0 to double
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%rcp = call double @llvm.amdgcn.rcp.f64(double %tmp1)
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%tmp2 = bitcast double %rcp to i64
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store i64 %tmp2, ptr addrspace(1) %gep
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ret void
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}
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; GCN-LABEL: {{^}}dpp64_rcp_unsupported_ctl:
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; GCN-COUNT-2: v_mov_b32_dpp v{{[0-9]+}}, v{{[0-9]+}} quad_perm:[1,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1{{$}}
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; GCN: v_rcp_f64_e32
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define amdgpu_kernel void @dpp64_rcp_unsupported_ctl(ptr addrspace(1) %arg, i64 %in1) {
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%id = tail call i32 @llvm.amdgcn.workitem.id.x()
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%gep = getelementptr inbounds i64, ptr addrspace(1) %arg, i32 %id
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%load = load i64, ptr addrspace(1) %gep
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%tmp0 = call i64 @llvm.amdgcn.update.dpp.i64(i64 %in1, i64 %load, i32 1, i32 15, i32 15, i1 1) #0
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%tmp1 = bitcast i64 %tmp0 to double
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%rcp = fdiv fast double 1.0, %tmp1
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%tmp2 = bitcast double %rcp to i64
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store i64 %tmp2, ptr addrspace(1) %gep
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ret void
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}
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; GCN-LABEL: {{^}}dpp64_div:
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; GCN: global_load_{{dwordx2|b64}} [[V:v\[[0-9:]+\]]],
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; DPPMOV64: v_mov_b64_dpp v[{{[0-9:]+}}], [[V]] row_newbcast:1 row_mask:0xf bank_mask:0xf bound_ctrl:1{{$}}
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; GFX90A-COUNT-2: v_mov_b32_dpp v{{[0-9]+}}, v{{[0-9]+}} row_newbcast:1 row_mask:0xf bank_mask:0xf bound_ctrl:1{{$}}
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; GFX10PLUS-COUNT-2: v_mov_b32_dpp v{{[0-9]+}}, v{{[0-9]+}} row_share:1 row_mask:0xf bank_mask:0xf bound_ctrl:1{{$}}
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; GCN: v_div_scale_f64
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; GCN: v_rcp_f64_e32
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define amdgpu_kernel void @dpp64_div(ptr addrspace(1) %arg, i64 %in1) {
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%id = tail call i32 @llvm.amdgcn.workitem.id.x()
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%gep = getelementptr inbounds i64, ptr addrspace(1) %arg, i32 %id
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%load = load i64, ptr addrspace(1) %gep
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%tmp0 = call i64 @llvm.amdgcn.update.dpp.i64(i64 %in1, i64 %load, i32 337, i32 15, i32 15, i1 1) #0
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%tmp1 = bitcast i64 %tmp0 to double
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%rcp = fdiv double 15.0, %tmp1
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%tmp2 = bitcast double %rcp to i64
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store i64 %tmp2, ptr addrspace(1) %gep
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ret void
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}
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; GCN-LABEL: {{^}}dpp64_loop:
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; GCN: v_mov_b32_dpp
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; DPP64: v_mov_b32_dpp
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; GFX90A: v_add_co_u32_e32
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; GFX90A: v_addc_co_u32_e32
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; GFX942: v_lshl_add_u64
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; GFX10PLUS: v_mov_b32_dpp
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; GFX10PLUS: v_add_co_u32
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; GFX10PLUS: v_add_co_ci_u32_e32
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define amdgpu_cs void @dpp64_loop(i64 %arg, i64 %val) {
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bb:
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br label %bb1
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bb1:
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%i = call i64 @llvm.amdgcn.update.dpp.i64(i64 poison, i64 %val, i32 0, i32 0, i32 0, i1 false)
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%i2 = add i64 %i, %arg
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%i3 = atomicrmw add ptr addrspace(1) null, i64 %i2 monotonic, align 8
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br label %bb1
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}
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declare i32 @llvm.amdgcn.workitem.id.x()
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declare i64 @llvm.amdgcn.update.dpp.i64(i64, i64, i32, i32, i32, i1) #0
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declare double @llvm.ceil.f64(double)
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declare double @llvm.amdgcn.rcp.f64(double)
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attributes #0 = { nounwind readnone convergent }
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