a33a84ee63
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test gfx940 and gfx941 are no longer supported. This is one of a series of PRs to remove them from the code base. This PR uses gfx942 instead of gfx940 and gfx941 in the test RUN-lines (unless there is already a RUN-line for gfx942). The only notable difference in the test output is that gfx942 does not force the use of sc0 and sc1 on stores while gfx940 and gfx941 do (cf. https://reviews.llvm.org/D149986). For SWDEV-512631
53 lines
2.3 KiB
YAML
53 lines
2.3 KiB
YAML
# RUN: llc -mtriple=amdgcn -mcpu=gfx90a -run-pass=gcn-dpp-combine -verify-machineinstrs -o - %s | FileCheck %s --check-prefix=GCN
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# RUN: llc -mtriple=amdgcn -mcpu=gfx942 -run-pass=gcn-dpp-combine -verify-machineinstrs -o - %s | FileCheck %s --check-prefix=GCN
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---
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# GCN-LABEL: name: dpp64_old_impdef
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# GCN: %3:vreg_64_align2 = V_CEIL_F64_dpp %1, 0, %0, 337, 15, 15, 1, implicit $mode, implicit $exec
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---
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name: dpp64_old_impdef
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tracksRegLiveness: true
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body: |
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bb.0:
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%0:vreg_64_align2 = IMPLICIT_DEF
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%1:vreg_64_align2 = IMPLICIT_DEF
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%2:vreg_64_align2 = V_MOV_B64_DPP_PSEUDO %1, %0, 337, 15, 15, 1, implicit $exec
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%3:vreg_64_align2 = V_CEIL_F64_e32 %2, implicit $mode, implicit $exec
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...
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# GCN-LABEL: name: dpp64_old_undef
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# GCN: %3:vreg_64_align2 = V_CEIL_F64_dpp undef %1:vreg_64_align2, 0, undef %2:vreg_64_align2, 337, 15, 15, 1, implicit $mode, implicit $exec
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---
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name: dpp64_old_undef
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tracksRegLiveness: true
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body: |
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bb.0:
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%2:vreg_64_align2 = V_MOV_B64_DPP_PSEUDO undef %1:vreg_64_align2, undef %0:vreg_64_align2, 337, 15, 15, 1, implicit $exec
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%3:vreg_64_align2 = V_CEIL_F64_e32 %2, implicit $mode, implicit $exec
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...
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# GCN-LABEL: name: dpp64_old_is_0
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# GCN: %3:vreg_64_align2 = V_CEIL_F64_dpp %4, 0, undef %2:vreg_64_align2, 337, 15, 15, 1, implicit $mode, implicit $exec
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name: dpp64_old_is_0
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tracksRegLiveness: true
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body: |
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bb.0:
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%1:vreg_64_align2 = V_MOV_B64_PSEUDO 0, implicit $exec
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%2:vreg_64_align2 = V_MOV_B64_DPP_PSEUDO undef %1, undef %0:vreg_64_align2, 337, 15, 15, 1, implicit $exec
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%3:vreg_64_align2 = V_CEIL_F64_e32 %2, implicit $mode, implicit $exec
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...
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# DPP64 does not support all control values and must be split to become legal
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# GCN-LABEL: name: dpp64_illegal_ctrl
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# GCN: %4:vgpr_32 = V_MOV_B32_dpp undef %1.sub0:vreg_64_align2, undef %2.sub0:vreg_64_align2, 1, 15, 15, 1, implicit $exec
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# GCN: %5:vgpr_32 = V_MOV_B32_dpp undef %1.sub1:vreg_64_align2, undef %2.sub1:vreg_64_align2, 1, 15, 15, 1, implicit $exec
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# GCN: %0:vreg_64_align2 = REG_SEQUENCE %4, %subreg.sub0, %5, %subreg.sub1
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# GCN: %3:vreg_64_align2 = V_CEIL_F64_e32 %0, implicit $mode, implicit $exec
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name: dpp64_illegal_ctrl
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tracksRegLiveness: true
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body: |
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bb.0:
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%2:vreg_64_align2 = V_MOV_B64_DPP_PSEUDO undef %1:vreg_64_align2, undef %0:vreg_64_align2, 1, 15, 15, 1, implicit $exec
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%3:vreg_64_align2 = V_CEIL_F64_e32 %2, implicit $mode, implicit $exec
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...
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