39bf765bb6
For most targets, the register class comes from the type so this makes no difference. For AMDGPU, the selected register class depends on the divergence of the value. For a constant phi input, this will always be false. The heuristic for whether to treat the value as a scalar or vector constant based on the uses would then incorrectly think this is a scalar use, when really the phi is a copy from S to V. This avoids an intermediate s_mov_b32 plus a copy in some cases. These would often, but not always, fold out in mi passes. This only adjusts the constant input case. It may make sense to do this for the non-constant case as well.
25 lines
833 B
LLVM
25 lines
833 B
LLVM
; RUN: llc -mtriple=amdgcn -stop-after=amdgpu-isel -verify-machineinstrs -o - %s | FileCheck %s
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; RUN: llc -mtriple=amdgcn -stop-after=amdgpu-isel -enable-new-pm -o - %s | FileCheck %s
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; CHECK-LABEL: vcopy_i1_undef
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; CHECK: [[IMPDEF0:%[0-9]+]]:vreg_1 = IMPLICIT_DEF
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; CHECK-NOT: COPY
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; CHECK: [[IMPDEF1:%[0-9]+]]:vreg_1 = IMPLICIT_DEF
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; CHECK-NOT: COPY [[IMPDEF0]]
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; CHECK-NOT: COPY [[IMPDEF1]]
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; CHECK: .false:
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define <2 x float> @vcopy_i1_undef(ptr addrspace(1) %p, i1 %c0) {
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entry:
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br i1 %c0, label %exit, label %false
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false:
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%x = load <2 x float>, ptr addrspace(1) %p
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%cmp = fcmp one <2 x float> %x, zeroinitializer
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br label %exit
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exit:
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%c = phi <2 x i1> [ undef, %entry ], [ %cmp, %false ]
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%ret = select <2 x i1> %c, <2 x float> <float 2.0, float 2.0>, <2 x float> <float 4.0, float 4.0>
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ret <2 x float> %ret
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}
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