39bf765bb6
For most targets, the register class comes from the type so this makes no difference. For AMDGPU, the selected register class depends on the divergence of the value. For a constant phi input, this will always be false. The heuristic for whether to treat the value as a scalar or vector constant based on the uses would then incorrectly think this is a scalar use, when really the phi is a copy from S to V. This avoids an intermediate s_mov_b32 plus a copy in some cases. These would often, but not always, fold out in mi passes. This only adjusts the constant input case. It may make sense to do this for the non-constant case as well.
132 lines
5.0 KiB
LLVM
132 lines
5.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck %s -check-prefix=GCN
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define amdgpu_cs void @if_then(ptr addrspace(8) inreg %input, ptr addrspace(8) inreg %output, <3 x i32> %LocalInvocationId) {
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; GCN-LABEL: if_then:
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; GCN: ; %bb.0: ; %.entry
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; GCN-NEXT: v_mov_b32_e32 v3, 0
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; GCN-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
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; GCN-NEXT: s_and_saveexec_b32 s0, vcc_lo
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; GCN-NEXT: ; %bb.1: ; %.bb0
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; GCN-NEXT: v_mov_b32_e32 v3, 1
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; GCN-NEXT: ; %bb.2: ; %.merge
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; GCN-NEXT: s_or_b32 exec_lo, exec_lo, s0
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; GCN-NEXT: v_cmp_lt_u32_e32 vcc_lo, 3, v0
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; GCN-NEXT: s_and_saveexec_b32 s0, vcc_lo
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; GCN-NEXT: s_cbranch_execz .LBB0_4
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; GCN-NEXT: ; %bb.3: ; %.then
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; GCN-NEXT: s_or_saveexec_b32 s1, -1
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; GCN-NEXT: v_cndmask_b32_e64 v1, 0, v3, s1
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; GCN-NEXT: v_mov_b32_e32 v2, 0
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; GCN-NEXT: v_mov_b32_dpp v2, v1 row_shr:1 row_mask:0xf bank_mask:0xf
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; GCN-NEXT: s_mov_b32 exec_lo, s1
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; GCN-NEXT: v_mov_b32_e32 v0, v2
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; GCN-NEXT: v_mov_b32_e32 v4, -1
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; GCN-NEXT: v_mov_b32_e32 v3, 0
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; GCN-NEXT: buffer_store_dword v4, v0, s[4:7], 0 offen
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; GCN-NEXT: .LBB0_4: ; %.end
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; GCN-NEXT: s_waitcnt_depctr 0xffe3
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; GCN-NEXT: s_or_b32 exec_lo, exec_lo, s0
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; GCN-NEXT: v_mov_b32_e32 v0, -1
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; GCN-NEXT: buffer_store_dword v0, v3, s[4:7], 0 offen
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; GCN-NEXT: s_endpgm
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.entry:
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%LocalInvocationId.i0 = extractelement <3 x i32> %LocalInvocationId, i32 0
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%.not10002 = icmp eq i32 %LocalInvocationId.i0, 0
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br i1 %.not10002, label %.merge, label %.bb0
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.bb0:
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br label %.merge
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.merge:
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%src = phi i32 [ 0, %.entry ], [ 1, %.bb0 ]
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%i530 = icmp ult i32 %LocalInvocationId.i0, 4
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br i1 %i530, label %.end, label %.then
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.then:
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%i562 = call i32 @llvm.amdgcn.set.inactive.i32(i32 %src, i32 0)
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%i563 = call i32 @llvm.amdgcn.update.dpp.i32(i32 0, i32 %i562, i32 273, i32 15, i32 15, i1 false)
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%i564 = call i32 @llvm.amdgcn.strict.wwm.i32(i32 %i563)
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call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 -1, ptr addrspace(8) %output, i32 %i564, i32 0, i32 0)
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br label %.end
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.end:
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%idx = phi i32 [ 0, %.then ], [ %src, %.merge ]
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call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 -1, ptr addrspace(8) %output, i32 %idx, i32 0, i32 0)
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ret void
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}
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define amdgpu_cs void @if_else_vgpr_opt(ptr addrspace(8) inreg %input, ptr addrspace(8) inreg %output, <3 x i32> %LocalInvocationId) {
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; GCN-LABEL: if_else_vgpr_opt:
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; GCN: ; %bb.0: ; %.entry
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; GCN-NEXT: v_mov_b32_e32 v3, 0
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; GCN-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
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; GCN-NEXT: s_and_saveexec_b32 s0, vcc_lo
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; GCN-NEXT: ; %bb.1: ; %.bb0
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; GCN-NEXT: v_mov_b32_e32 v3, 1
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; GCN-NEXT: ; %bb.2: ; %.merge
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; GCN-NEXT: s_or_b32 exec_lo, exec_lo, s0
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; GCN-NEXT: v_cmp_lt_u32_e32 vcc_lo, 3, v0
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; GCN-NEXT: s_and_saveexec_b32 s0, vcc_lo
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; GCN-NEXT: s_xor_b32 s0, exec_lo, s0
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; GCN-NEXT: s_cbranch_execnz .LBB1_5
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; GCN-NEXT: ; %bb.3: ; %Flow
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; GCN-NEXT: s_andn2_saveexec_b32 s0, s0
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; GCN-NEXT: s_cbranch_execnz .LBB1_6
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; GCN-NEXT: .LBB1_4: ; %.end
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; GCN-NEXT: s_endpgm
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; GCN-NEXT: .LBB1_5: ; %.else
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; GCN-NEXT: s_or_saveexec_b32 s1, -1
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; GCN-NEXT: v_mov_b32_e32 v1, 0
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; GCN-NEXT: v_cndmask_b32_e64 v2, 0, v3, s1
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; GCN-NEXT: v_mov_b32_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf
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; GCN-NEXT: s_mov_b32 exec_lo, s1
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; GCN-NEXT: v_mov_b32_e32 v0, v1
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; GCN-NEXT: v_mov_b32_e32 v3, -1
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; GCN-NEXT: buffer_store_dword v3, v0, s[4:7], 0 offen
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; GCN-NEXT: ; implicit-def: $vgpr3
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; GCN-NEXT: s_andn2_saveexec_b32 s0, s0
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; GCN-NEXT: s_cbranch_execz .LBB1_4
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; GCN-NEXT: .LBB1_6: ; %.then
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; GCN-NEXT: v_mov_b32_e32 v0, -1
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; GCN-NEXT: buffer_store_dword v0, v3, s[4:7], 0 offen
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; GCN-NEXT: s_endpgm
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.entry:
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%LocalInvocationId.i0 = extractelement <3 x i32> %LocalInvocationId, i32 0
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%.not10002 = icmp eq i32 %LocalInvocationId.i0, 0
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br i1 %.not10002, label %.merge, label %.bb0
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.bb0:
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br label %.merge
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.merge:
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%src = phi i32 [ 0, %.entry ], [ 1, %.bb0 ]
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%i530 = icmp ult i32 %LocalInvocationId.i0, 4
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br i1 %i530, label %.then, label %.else
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.then:
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call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 -1, ptr addrspace(8) %output, i32 %src, i32 0, i32 0)
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br label %.end
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.else:
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%i562 = call i32 @llvm.amdgcn.set.inactive.i32(i32 %src, i32 0)
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%i563 = call i32 @llvm.amdgcn.update.dpp.i32(i32 0, i32 %i562, i32 273, i32 15, i32 15, i1 false)
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%i564 = call i32 @llvm.amdgcn.strict.wwm.i32(i32 %i563)
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call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 -1, ptr addrspace(8) %output, i32 %i564, i32 0, i32 0)
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br label %.end
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.end:
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ret void
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}
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declare i32 @llvm.amdgcn.set.inactive.i32(i32, i32) #0
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declare i32 @llvm.amdgcn.update.dpp.i32(i32, i32, i32, i32, i32, i1) #0
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declare i32 @llvm.amdgcn.strict.wwm.i32(i32) #1
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declare void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32, ptr addrspace(8), i32, i32 immarg, i32 immarg) #2
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attributes #0 = { convergent nounwind readnone willreturn }
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attributes #1 = { convergent nounwind readnone speculatable willreturn }
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attributes #2 = { nounwind willreturn writeonly }
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