58a88001f3
This fixes the handling of subregister extract copies. This will allow AMDGPU to remove its implementation of shouldRewriteCopySrc, which exists as a 10 year old workaround to this bug. peephole-opt-fold-reg-sequence-subreg.mir will show the expected improvement once the custom implementation is removed. The copy coalescing processing here is overly abstracted from what's actually happening. Previously when visiting coalescable copy-like instructions, we would parse the sources one at a time and then pass the def of the root instruction into findNextSource. This means that the first thing the new ValueTracker constructed would do is getVRegDef to find the instruction we are currently processing. This adds an unnecessary step, placing a useless entry in the RewriteMap, and required skipping the no-op case where getNewSource would return the original source operand. This was a problem since in the case of a subregister extract, shouldRewriteCopySource would always say that it is useful to rewrite and the use-def chain walk would abort, returning the original operand. Move the process to start looking at the source operand to begin with. This does not fix the confused handling in the uncoalescable copy case which is proving to be more difficult. Some currently handled cases have multiple defs from a single source, and other handled cases have 0 input operands. It would be simpler if this was implemented with isCopyLikeInstr, rather than guessing at the operand structure as it does now. There are some improvements and some regressions. The regressions appear to be downstream issues for the most part. One of the uglier regressions is in PPC, where a sequence of insert_subrgs is used to build registers. I opened #125502 to use reg_sequence instead, which may help. The worst regression is an absurd SPARC testcase using a <251 x fp128>, which uses a very long chain of insert_subregs. We need improved subregister handling locally in PeepholeOptimizer, and other pasess like MachineCSE to fix some of the other regressions. We should handle subregister composes and folding more indexes into insert_subreg and reg_sequence.
623 lines
21 KiB
LLVM
623 lines
21 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
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; RUN: -disable-auto-paired-vec-st=false < %s | FileCheck %s \
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; RUN: --check-prefix=LE-PAIRED
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
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; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names \
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; RUN: -ppc-vsr-nums-as-vr -disable-auto-paired-vec-st=false < %s | \
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; RUN: FileCheck %s --check-prefix=BE-PAIRED
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; RUN: llc -verify-machineinstrs -mcpu=pwr9 -ppc-vsr-nums-as-vr \
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; RUN: -ppc-asm-full-reg-names -mtriple=powerpc64le-unknown-linux-gnu < %s \
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; RUN: | FileCheck %s --check-prefix=LE-PWR9
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; RUN: llc -verify-machineinstrs -mcpu=pwr8 -ppc-vsr-nums-as-vr \
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; RUN: -ppc-asm-full-reg-names -mtriple=powerpc64le-unknown-linux-gnu < %s \
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; RUN: | FileCheck %s --check-prefix=LE-PWR8
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; RUN: llc -verify-machineinstrs -mcpu=pwr9 -ppc-vsr-nums-as-vr \
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; RUN: -ppc-asm-full-reg-names -mtriple=powerpc64-unknown-linux-gnu < %s \
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; RUN: | FileCheck %s --check-prefix=BE-PWR9
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; RUN: llc -verify-machineinstrs -mcpu=pwr8 -ppc-vsr-nums-as-vr \
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; RUN: -ppc-asm-full-reg-names -mtriple=powerpc64-unknown-linux-gnu < %s \
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; RUN: | FileCheck %s --check-prefix=BE-PWR8
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@f = common dso_local local_unnamed_addr global <512 x i1> zeroinitializer, align 16
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@g = common dso_local local_unnamed_addr global <256 x i1> zeroinitializer, align 16
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define dso_local void @testLdSt(i64 %SrcIdx, i64 %DstIdx) {
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; LE-PAIRED-LABEL: testLdSt:
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; LE-PAIRED: # %bb.0: # %entry
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; LE-PAIRED-NEXT: plxv vs1, f@PCREL+96(0), 1
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; LE-PAIRED-NEXT: plxv vs0, f@PCREL+112(0), 1
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; LE-PAIRED-NEXT: plxv vs3, f@PCREL+64(0), 1
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; LE-PAIRED-NEXT: plxv vs2, f@PCREL+80(0), 1
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; LE-PAIRED-NEXT: pstxv vs0, f@PCREL+176(0), 1
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; LE-PAIRED-NEXT: pstxv vs1, f@PCREL+160(0), 1
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; LE-PAIRED-NEXT: pstxv vs2, f@PCREL+144(0), 1
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; LE-PAIRED-NEXT: pstxv vs3, f@PCREL+128(0), 1
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; LE-PAIRED-NEXT: blr
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;
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; BE-PAIRED-LABEL: testLdSt:
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; BE-PAIRED: # %bb.0: # %entry
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; BE-PAIRED-NEXT: addis r3, r2, f@toc@ha
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; BE-PAIRED-NEXT: addi r3, r3, f@toc@l
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; BE-PAIRED-NEXT: lxv vs1, 80(r3)
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; BE-PAIRED-NEXT: lxv vs0, 64(r3)
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; BE-PAIRED-NEXT: lxv vs3, 112(r3)
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; BE-PAIRED-NEXT: lxv vs2, 96(r3)
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; BE-PAIRED-NEXT: stxv vs1, 144(r3)
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; BE-PAIRED-NEXT: stxv vs0, 128(r3)
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; BE-PAIRED-NEXT: stxv vs3, 176(r3)
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; BE-PAIRED-NEXT: stxv vs2, 160(r3)
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; BE-PAIRED-NEXT: blr
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;
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; LE-PWR9-LABEL: testLdSt:
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; LE-PWR9: # %bb.0: # %entry
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; LE-PWR9-NEXT: addis r3, r2, f@toc@ha
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; LE-PWR9-NEXT: addi r3, r3, f@toc@l
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; LE-PWR9-NEXT: lxv vs1, 96(r3)
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; LE-PWR9-NEXT: lxv vs0, 64(r3)
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; LE-PWR9-NEXT: lxv vs2, 112(r3)
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; LE-PWR9-NEXT: stxv vs1, 160(r3)
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; LE-PWR9-NEXT: lxv vs1, 80(r3)
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; LE-PWR9-NEXT: stxv vs2, 176(r3)
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; LE-PWR9-NEXT: stxv vs0, 128(r3)
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; LE-PWR9-NEXT: stxv vs1, 144(r3)
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; LE-PWR9-NEXT: blr
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;
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; LE-PWR8-LABEL: testLdSt:
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; LE-PWR8: # %bb.0: # %entry
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; LE-PWR8-NEXT: addis r3, r2, f@toc@ha
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; LE-PWR8-NEXT: li r4, 64
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; LE-PWR8-NEXT: addi r3, r3, f@toc@l
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; LE-PWR8-NEXT: lxvd2x vs0, r3, r4
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; LE-PWR8-NEXT: li r4, 80
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; LE-PWR8-NEXT: lxvd2x vs1, r3, r4
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; LE-PWR8-NEXT: li r4, 96
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; LE-PWR8-NEXT: lxvd2x vs2, r3, r4
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; LE-PWR8-NEXT: li r4, 112
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; LE-PWR8-NEXT: lxvd2x vs3, r3, r4
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; LE-PWR8-NEXT: li r4, 176
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; LE-PWR8-NEXT: stxvd2x vs3, r3, r4
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; LE-PWR8-NEXT: li r4, 160
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; LE-PWR8-NEXT: stxvd2x vs2, r3, r4
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; LE-PWR8-NEXT: li r4, 144
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; LE-PWR8-NEXT: stxvd2x vs1, r3, r4
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; LE-PWR8-NEXT: li r4, 128
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; LE-PWR8-NEXT: stxvd2x vs0, r3, r4
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; LE-PWR8-NEXT: blr
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;
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; BE-PWR9-LABEL: testLdSt:
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; BE-PWR9: # %bb.0: # %entry
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; BE-PWR9-NEXT: addis r3, r2, f@toc@ha
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; BE-PWR9-NEXT: addi r3, r3, f@toc@l
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; BE-PWR9-NEXT: lxv vs1, 96(r3)
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; BE-PWR9-NEXT: lxv vs0, 64(r3)
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; BE-PWR9-NEXT: lxv vs2, 112(r3)
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; BE-PWR9-NEXT: stxv vs1, 160(r3)
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; BE-PWR9-NEXT: lxv vs1, 80(r3)
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; BE-PWR9-NEXT: stxv vs2, 176(r3)
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; BE-PWR9-NEXT: stxv vs0, 128(r3)
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; BE-PWR9-NEXT: stxv vs1, 144(r3)
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; BE-PWR9-NEXT: blr
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;
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; BE-PWR8-LABEL: testLdSt:
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; BE-PWR8: # %bb.0: # %entry
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; BE-PWR8-NEXT: addis r3, r2, f@toc@ha
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; BE-PWR8-NEXT: li r4, 64
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; BE-PWR8-NEXT: addi r3, r3, f@toc@l
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; BE-PWR8-NEXT: lxvd2x vs0, r3, r4
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; BE-PWR8-NEXT: li r4, 80
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; BE-PWR8-NEXT: lxvd2x vs1, r3, r4
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; BE-PWR8-NEXT: li r4, 96
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; BE-PWR8-NEXT: lxvd2x vs2, r3, r4
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; BE-PWR8-NEXT: li r4, 112
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; BE-PWR8-NEXT: lxvd2x vs3, r3, r4
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; BE-PWR8-NEXT: li r4, 176
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; BE-PWR8-NEXT: stxvd2x vs3, r3, r4
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; BE-PWR8-NEXT: li r4, 160
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; BE-PWR8-NEXT: stxvd2x vs2, r3, r4
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; BE-PWR8-NEXT: li r4, 144
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; BE-PWR8-NEXT: stxvd2x vs1, r3, r4
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; BE-PWR8-NEXT: li r4, 128
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; BE-PWR8-NEXT: stxvd2x vs0, r3, r4
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; BE-PWR8-NEXT: blr
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entry:
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%arrayidx = getelementptr inbounds <512 x i1>, ptr @f, i64 1
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%0 = load <512 x i1>, ptr %arrayidx, align 64
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%arrayidx1 = getelementptr inbounds <512 x i1>, ptr @f, i64 2
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store <512 x i1> %0, ptr %arrayidx1, align 64
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ret void
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}
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define dso_local void @testXLdSt(i64 %SrcIdx, i64 %DstIdx) {
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; LE-PAIRED-LABEL: testXLdSt:
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; LE-PAIRED: # %bb.0: # %entry
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; LE-PAIRED-NEXT: paddi r5, 0, f@PCREL, 1
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; LE-PAIRED-NEXT: sldi r3, r3, 6
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; LE-PAIRED-NEXT: add r6, r5, r3
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; LE-PAIRED-NEXT: lxv vs1, 32(r6)
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; LE-PAIRED-NEXT: lxv vs0, 48(r6)
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; LE-PAIRED-NEXT: lxvx vs3, r5, r3
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; LE-PAIRED-NEXT: lxv vs2, 16(r6)
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; LE-PAIRED-NEXT: sldi r3, r4, 6
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; LE-PAIRED-NEXT: add r4, r5, r3
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; LE-PAIRED-NEXT: stxvx vs3, r5, r3
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; LE-PAIRED-NEXT: stxv vs0, 48(r4)
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; LE-PAIRED-NEXT: stxv vs1, 32(r4)
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; LE-PAIRED-NEXT: stxv vs2, 16(r4)
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; LE-PAIRED-NEXT: blr
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;
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; BE-PAIRED-LABEL: testXLdSt:
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; BE-PAIRED: # %bb.0: # %entry
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; BE-PAIRED-NEXT: addis r5, r2, f@toc@ha
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; BE-PAIRED-NEXT: addi r5, r5, f@toc@l
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; BE-PAIRED-NEXT: sldi r3, r3, 6
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; BE-PAIRED-NEXT: add r6, r5, r3
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; BE-PAIRED-NEXT: lxvx vs0, r5, r3
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; BE-PAIRED-NEXT: sldi r3, r4, 6
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; BE-PAIRED-NEXT: add r4, r5, r3
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; BE-PAIRED-NEXT: lxv vs1, 16(r6)
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; BE-PAIRED-NEXT: lxv vs3, 48(r6)
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; BE-PAIRED-NEXT: lxv vs2, 32(r6)
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; BE-PAIRED-NEXT: stxvx vs0, r5, r3
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; BE-PAIRED-NEXT: stxv vs1, 16(r4)
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; BE-PAIRED-NEXT: stxv vs3, 48(r4)
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; BE-PAIRED-NEXT: stxv vs2, 32(r4)
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; BE-PAIRED-NEXT: blr
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;
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; LE-PWR9-LABEL: testXLdSt:
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; LE-PWR9: # %bb.0: # %entry
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; LE-PWR9-NEXT: addis r5, r2, f@toc@ha
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; LE-PWR9-NEXT: sldi r3, r3, 6
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; LE-PWR9-NEXT: addi r5, r5, f@toc@l
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; LE-PWR9-NEXT: add r6, r5, r3
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; LE-PWR9-NEXT: lxvx vs3, r5, r3
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; LE-PWR9-NEXT: sldi r3, r4, 6
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; LE-PWR9-NEXT: lxv vs0, 16(r6)
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; LE-PWR9-NEXT: lxv vs1, 32(r6)
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; LE-PWR9-NEXT: lxv vs2, 48(r6)
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; LE-PWR9-NEXT: stxvx vs3, r5, r3
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; LE-PWR9-NEXT: add r3, r5, r3
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; LE-PWR9-NEXT: stxv vs2, 48(r3)
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; LE-PWR9-NEXT: stxv vs1, 32(r3)
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; LE-PWR9-NEXT: stxv vs0, 16(r3)
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; LE-PWR9-NEXT: blr
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;
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; LE-PWR8-LABEL: testXLdSt:
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; LE-PWR8: # %bb.0: # %entry
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; LE-PWR8-NEXT: addis r5, r2, f@toc@ha
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; LE-PWR8-NEXT: sldi r3, r3, 6
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; LE-PWR8-NEXT: li r7, 16
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; LE-PWR8-NEXT: li r8, 32
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; LE-PWR8-NEXT: li r9, 48
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; LE-PWR8-NEXT: addi r5, r5, f@toc@l
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; LE-PWR8-NEXT: add r6, r5, r3
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; LE-PWR8-NEXT: lxvd2x vs3, r5, r3
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; LE-PWR8-NEXT: sldi r3, r4, 6
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; LE-PWR8-NEXT: lxvd2x vs0, r6, r7
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; LE-PWR8-NEXT: lxvd2x vs1, r6, r8
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; LE-PWR8-NEXT: lxvd2x vs2, r6, r9
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; LE-PWR8-NEXT: stxvd2x vs3, r5, r3
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; LE-PWR8-NEXT: add r3, r5, r3
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; LE-PWR8-NEXT: stxvd2x vs2, r3, r9
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; LE-PWR8-NEXT: stxvd2x vs1, r3, r8
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; LE-PWR8-NEXT: stxvd2x vs0, r3, r7
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; LE-PWR8-NEXT: blr
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;
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; BE-PWR9-LABEL: testXLdSt:
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; BE-PWR9: # %bb.0: # %entry
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; BE-PWR9-NEXT: addis r5, r2, f@toc@ha
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; BE-PWR9-NEXT: sldi r3, r3, 6
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; BE-PWR9-NEXT: addi r5, r5, f@toc@l
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; BE-PWR9-NEXT: add r6, r5, r3
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; BE-PWR9-NEXT: lxvx vs3, r5, r3
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; BE-PWR9-NEXT: sldi r3, r4, 6
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; BE-PWR9-NEXT: lxv vs0, 16(r6)
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; BE-PWR9-NEXT: lxv vs1, 32(r6)
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; BE-PWR9-NEXT: lxv vs2, 48(r6)
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; BE-PWR9-NEXT: stxvx vs3, r5, r3
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; BE-PWR9-NEXT: add r3, r5, r3
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; BE-PWR9-NEXT: stxv vs2, 48(r3)
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; BE-PWR9-NEXT: stxv vs1, 32(r3)
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; BE-PWR9-NEXT: stxv vs0, 16(r3)
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; BE-PWR9-NEXT: blr
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;
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; BE-PWR8-LABEL: testXLdSt:
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; BE-PWR8: # %bb.0: # %entry
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; BE-PWR8-NEXT: addis r5, r2, f@toc@ha
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; BE-PWR8-NEXT: sldi r3, r3, 6
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; BE-PWR8-NEXT: li r7, 32
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; BE-PWR8-NEXT: li r8, 48
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; BE-PWR8-NEXT: sldi r4, r4, 6
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; BE-PWR8-NEXT: addi r5, r5, f@toc@l
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; BE-PWR8-NEXT: add r6, r5, r3
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; BE-PWR8-NEXT: lxvd2x vs0, r5, r3
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; BE-PWR8-NEXT: li r3, 16
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; BE-PWR8-NEXT: lxvd2x vs1, r6, r3
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; BE-PWR8-NEXT: lxvd2x vs2, r6, r7
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; BE-PWR8-NEXT: lxvd2x vs3, r6, r8
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; BE-PWR8-NEXT: add r6, r5, r4
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; BE-PWR8-NEXT: stxvd2x vs0, r5, r4
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; BE-PWR8-NEXT: stxvd2x vs3, r6, r8
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; BE-PWR8-NEXT: stxvd2x vs2, r6, r7
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; BE-PWR8-NEXT: stxvd2x vs1, r6, r3
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; BE-PWR8-NEXT: blr
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entry:
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%arrayidx = getelementptr inbounds <512 x i1>, ptr @f, i64 %SrcIdx
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%0 = load <512 x i1>, ptr %arrayidx, align 64
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%arrayidx1 = getelementptr inbounds <512 x i1>, ptr @f, i64 %DstIdx
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store <512 x i1> %0, ptr %arrayidx1, align 64
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ret void
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}
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define dso_local void @testUnalignedLdSt() {
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; LE-PAIRED-LABEL: testUnalignedLdSt:
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; LE-PAIRED: # %bb.0: # %entry
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; LE-PAIRED-NEXT: plxv vs1, f@PCREL+43(0), 1
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; LE-PAIRED-NEXT: plxv vs0, f@PCREL+59(0), 1
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; LE-PAIRED-NEXT: plxv vs3, f@PCREL+11(0), 1
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; LE-PAIRED-NEXT: plxv vs2, f@PCREL+27(0), 1
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; LE-PAIRED-NEXT: pstxv vs0, f@PCREL+67(0), 1
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; LE-PAIRED-NEXT: pstxv vs1, f@PCREL+51(0), 1
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; LE-PAIRED-NEXT: pstxv vs2, f@PCREL+35(0), 1
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; LE-PAIRED-NEXT: pstxv vs3, f@PCREL+19(0), 1
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; LE-PAIRED-NEXT: blr
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;
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; BE-PAIRED-LABEL: testUnalignedLdSt:
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; BE-PAIRED: # %bb.0: # %entry
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; BE-PAIRED-NEXT: addis r3, r2, f@toc@ha
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; BE-PAIRED-NEXT: addi r3, r3, f@toc@l
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; BE-PAIRED-NEXT: plxv vs1, 27(r3), 0
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; BE-PAIRED-NEXT: plxv vs0, 11(r3), 0
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; BE-PAIRED-NEXT: plxv vs3, 59(r3), 0
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; BE-PAIRED-NEXT: plxv vs2, 43(r3), 0
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; BE-PAIRED-NEXT: pstxv vs1, 35(r3), 0
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; BE-PAIRED-NEXT: pstxv vs0, 19(r3), 0
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; BE-PAIRED-NEXT: pstxv vs3, 67(r3), 0
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; BE-PAIRED-NEXT: pstxv vs2, 51(r3), 0
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; BE-PAIRED-NEXT: blr
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;
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; LE-PWR9-LABEL: testUnalignedLdSt:
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; LE-PWR9: # %bb.0: # %entry
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; LE-PWR9-NEXT: addis r3, r2, f@toc@ha
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; LE-PWR9-NEXT: li r4, 11
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; LE-PWR9-NEXT: addi r3, r3, f@toc@l
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; LE-PWR9-NEXT: lxvx vs0, r3, r4
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; LE-PWR9-NEXT: li r4, 27
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; LE-PWR9-NEXT: lxvx vs1, r3, r4
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; LE-PWR9-NEXT: li r4, 43
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; LE-PWR9-NEXT: lxvx vs2, r3, r4
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; LE-PWR9-NEXT: li r4, 59
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; LE-PWR9-NEXT: lxvx vs3, r3, r4
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; LE-PWR9-NEXT: li r4, 67
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; LE-PWR9-NEXT: stxvx vs3, r3, r4
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; LE-PWR9-NEXT: li r4, 51
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; LE-PWR9-NEXT: stxvx vs2, r3, r4
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; LE-PWR9-NEXT: li r4, 35
|
|
; LE-PWR9-NEXT: stxvx vs1, r3, r4
|
|
; LE-PWR9-NEXT: li r4, 19
|
|
; LE-PWR9-NEXT: stxvx vs0, r3, r4
|
|
; LE-PWR9-NEXT: blr
|
|
;
|
|
; LE-PWR8-LABEL: testUnalignedLdSt:
|
|
; LE-PWR8: # %bb.0: # %entry
|
|
; LE-PWR8-NEXT: addis r3, r2, f@toc@ha
|
|
; LE-PWR8-NEXT: li r4, 11
|
|
; LE-PWR8-NEXT: addi r3, r3, f@toc@l
|
|
; LE-PWR8-NEXT: lxvd2x vs0, r3, r4
|
|
; LE-PWR8-NEXT: li r4, 27
|
|
; LE-PWR8-NEXT: lxvd2x vs1, r3, r4
|
|
; LE-PWR8-NEXT: li r4, 43
|
|
; LE-PWR8-NEXT: lxvd2x vs2, r3, r4
|
|
; LE-PWR8-NEXT: li r4, 59
|
|
; LE-PWR8-NEXT: lxvd2x vs3, r3, r4
|
|
; LE-PWR8-NEXT: li r4, 67
|
|
; LE-PWR8-NEXT: stxvd2x vs3, r3, r4
|
|
; LE-PWR8-NEXT: li r4, 51
|
|
; LE-PWR8-NEXT: stxvd2x vs2, r3, r4
|
|
; LE-PWR8-NEXT: li r4, 35
|
|
; LE-PWR8-NEXT: stxvd2x vs1, r3, r4
|
|
; LE-PWR8-NEXT: li r4, 19
|
|
; LE-PWR8-NEXT: stxvd2x vs0, r3, r4
|
|
; LE-PWR8-NEXT: blr
|
|
;
|
|
; BE-PWR9-LABEL: testUnalignedLdSt:
|
|
; BE-PWR9: # %bb.0: # %entry
|
|
; BE-PWR9-NEXT: addis r3, r2, f@toc@ha
|
|
; BE-PWR9-NEXT: li r4, 11
|
|
; BE-PWR9-NEXT: addi r3, r3, f@toc@l
|
|
; BE-PWR9-NEXT: lxvx vs0, r3, r4
|
|
; BE-PWR9-NEXT: li r4, 27
|
|
; BE-PWR9-NEXT: lxvx vs1, r3, r4
|
|
; BE-PWR9-NEXT: li r4, 43
|
|
; BE-PWR9-NEXT: lxvx vs2, r3, r4
|
|
; BE-PWR9-NEXT: li r4, 59
|
|
; BE-PWR9-NEXT: lxvx vs3, r3, r4
|
|
; BE-PWR9-NEXT: li r4, 67
|
|
; BE-PWR9-NEXT: stxvx vs3, r3, r4
|
|
; BE-PWR9-NEXT: li r4, 51
|
|
; BE-PWR9-NEXT: stxvx vs2, r3, r4
|
|
; BE-PWR9-NEXT: li r4, 35
|
|
; BE-PWR9-NEXT: stxvx vs1, r3, r4
|
|
; BE-PWR9-NEXT: li r4, 19
|
|
; BE-PWR9-NEXT: stxvx vs0, r3, r4
|
|
; BE-PWR9-NEXT: blr
|
|
;
|
|
; BE-PWR8-LABEL: testUnalignedLdSt:
|
|
; BE-PWR8: # %bb.0: # %entry
|
|
; BE-PWR8-NEXT: addis r3, r2, f@toc@ha
|
|
; BE-PWR8-NEXT: li r4, 11
|
|
; BE-PWR8-NEXT: addi r3, r3, f@toc@l
|
|
; BE-PWR8-NEXT: lxvd2x vs0, r3, r4
|
|
; BE-PWR8-NEXT: li r4, 27
|
|
; BE-PWR8-NEXT: lxvd2x vs1, r3, r4
|
|
; BE-PWR8-NEXT: li r4, 43
|
|
; BE-PWR8-NEXT: lxvd2x vs2, r3, r4
|
|
; BE-PWR8-NEXT: li r4, 59
|
|
; BE-PWR8-NEXT: lxvd2x vs3, r3, r4
|
|
; BE-PWR8-NEXT: li r4, 67
|
|
; BE-PWR8-NEXT: stxvd2x vs3, r3, r4
|
|
; BE-PWR8-NEXT: li r4, 51
|
|
; BE-PWR8-NEXT: stxvd2x vs2, r3, r4
|
|
; BE-PWR8-NEXT: li r4, 35
|
|
; BE-PWR8-NEXT: stxvd2x vs1, r3, r4
|
|
; BE-PWR8-NEXT: li r4, 19
|
|
; BE-PWR8-NEXT: stxvd2x vs0, r3, r4
|
|
; BE-PWR8-NEXT: blr
|
|
entry:
|
|
%add.ptr = getelementptr inbounds i8, ptr @f, i64 11
|
|
%add.ptr1 = getelementptr inbounds i8, ptr @f, i64 19
|
|
%0 = load <512 x i1>, ptr %add.ptr, align 64
|
|
store <512 x i1> %0, ptr %add.ptr1, align 64
|
|
ret void
|
|
}
|
|
|
|
define dso_local void @testLdStPair(i64 %SrcIdx, i64 %DstIdx) {
|
|
; LE-PAIRED-LABEL: testLdStPair:
|
|
; LE-PAIRED: # %bb.0: # %entry
|
|
; LE-PAIRED-NEXT: plxv v3, g@PCREL+32(0), 1
|
|
; LE-PAIRED-NEXT: plxv vs0, g@PCREL+48(0), 1
|
|
; LE-PAIRED-NEXT: pstxv vs0, g@PCREL+80(0), 1
|
|
; LE-PAIRED-NEXT: pstxv v3, g@PCREL+64(0), 1
|
|
; LE-PAIRED-NEXT: blr
|
|
;
|
|
; BE-PAIRED-LABEL: testLdStPair:
|
|
; BE-PAIRED: # %bb.0: # %entry
|
|
; BE-PAIRED-NEXT: addis r3, r2, g@toc@ha
|
|
; BE-PAIRED-NEXT: addi r3, r3, g@toc@l
|
|
; BE-PAIRED-NEXT: lxv v3, 48(r3)
|
|
; BE-PAIRED-NEXT: lxv vs0, 32(r3)
|
|
; BE-PAIRED-NEXT: stxv v3, 80(r3)
|
|
; BE-PAIRED-NEXT: stxv vs0, 64(r3)
|
|
; BE-PAIRED-NEXT: blr
|
|
;
|
|
; LE-PWR9-LABEL: testLdStPair:
|
|
; LE-PWR9: # %bb.0: # %entry
|
|
; LE-PWR9-NEXT: addis r3, r2, g@toc@ha
|
|
; LE-PWR9-NEXT: addi r3, r3, g@toc@l
|
|
; LE-PWR9-NEXT: lxv vs0, 32(r3)
|
|
; LE-PWR9-NEXT: lxv vs1, 48(r3)
|
|
; LE-PWR9-NEXT: stxv vs1, 80(r3)
|
|
; LE-PWR9-NEXT: stxv vs0, 64(r3)
|
|
; LE-PWR9-NEXT: blr
|
|
;
|
|
; LE-PWR8-LABEL: testLdStPair:
|
|
; LE-PWR8: # %bb.0: # %entry
|
|
; LE-PWR8-NEXT: addis r3, r2, g@toc@ha
|
|
; LE-PWR8-NEXT: li r4, 32
|
|
; LE-PWR8-NEXT: addi r3, r3, g@toc@l
|
|
; LE-PWR8-NEXT: lxvd2x vs0, r3, r4
|
|
; LE-PWR8-NEXT: li r4, 48
|
|
; LE-PWR8-NEXT: lxvd2x vs1, r3, r4
|
|
; LE-PWR8-NEXT: li r4, 80
|
|
; LE-PWR8-NEXT: stxvd2x vs1, r3, r4
|
|
; LE-PWR8-NEXT: li r4, 64
|
|
; LE-PWR8-NEXT: stxvd2x vs0, r3, r4
|
|
; LE-PWR8-NEXT: blr
|
|
;
|
|
; BE-PWR9-LABEL: testLdStPair:
|
|
; BE-PWR9: # %bb.0: # %entry
|
|
; BE-PWR9-NEXT: addis r3, r2, g@toc@ha
|
|
; BE-PWR9-NEXT: addi r3, r3, g@toc@l
|
|
; BE-PWR9-NEXT: lxv vs0, 32(r3)
|
|
; BE-PWR9-NEXT: lxv vs1, 48(r3)
|
|
; BE-PWR9-NEXT: stxv vs1, 80(r3)
|
|
; BE-PWR9-NEXT: stxv vs0, 64(r3)
|
|
; BE-PWR9-NEXT: blr
|
|
;
|
|
; BE-PWR8-LABEL: testLdStPair:
|
|
; BE-PWR8: # %bb.0: # %entry
|
|
; BE-PWR8-NEXT: addis r3, r2, g@toc@ha
|
|
; BE-PWR8-NEXT: li r4, 32
|
|
; BE-PWR8-NEXT: addi r3, r3, g@toc@l
|
|
; BE-PWR8-NEXT: lxvd2x vs0, r3, r4
|
|
; BE-PWR8-NEXT: li r4, 48
|
|
; BE-PWR8-NEXT: lxvd2x vs1, r3, r4
|
|
; BE-PWR8-NEXT: li r4, 80
|
|
; BE-PWR8-NEXT: stxvd2x vs1, r3, r4
|
|
; BE-PWR8-NEXT: li r4, 64
|
|
; BE-PWR8-NEXT: stxvd2x vs0, r3, r4
|
|
; BE-PWR8-NEXT: blr
|
|
entry:
|
|
%arrayidx = getelementptr inbounds <256 x i1>, ptr @g, i64 1
|
|
%0 = load <256 x i1>, ptr %arrayidx, align 64
|
|
%arrayidx1 = getelementptr inbounds <256 x i1>, ptr @g, i64 2
|
|
store <256 x i1> %0, ptr %arrayidx1, align 64
|
|
ret void
|
|
}
|
|
|
|
define dso_local void @testXLdStPair(i64 %SrcIdx, i64 %DstIdx) {
|
|
; LE-PAIRED-LABEL: testXLdStPair:
|
|
; LE-PAIRED: # %bb.0: # %entry
|
|
; LE-PAIRED-NEXT: sldi r3, r3, 5
|
|
; LE-PAIRED-NEXT: paddi r5, 0, g@PCREL, 1
|
|
; LE-PAIRED-NEXT: add r6, r5, r3
|
|
; LE-PAIRED-NEXT: lxvx v3, r5, r3
|
|
; LE-PAIRED-NEXT: sldi r3, r4, 5
|
|
; LE-PAIRED-NEXT: add r4, r5, r3
|
|
; LE-PAIRED-NEXT: lxv vs0, 16(r6)
|
|
; LE-PAIRED-NEXT: stxvx v3, r5, r3
|
|
; LE-PAIRED-NEXT: stxv vs0, 16(r4)
|
|
; LE-PAIRED-NEXT: blr
|
|
;
|
|
; BE-PAIRED-LABEL: testXLdStPair:
|
|
; BE-PAIRED: # %bb.0: # %entry
|
|
; BE-PAIRED-NEXT: addis r5, r2, g@toc@ha
|
|
; BE-PAIRED-NEXT: sldi r3, r3, 5
|
|
; BE-PAIRED-NEXT: addi r5, r5, g@toc@l
|
|
; BE-PAIRED-NEXT: add r6, r5, r3
|
|
; BE-PAIRED-NEXT: lxvx vs0, r5, r3
|
|
; BE-PAIRED-NEXT: sldi r3, r4, 5
|
|
; BE-PAIRED-NEXT: add r4, r5, r3
|
|
; BE-PAIRED-NEXT: lxv v3, 16(r6)
|
|
; BE-PAIRED-NEXT: stxvx vs0, r5, r3
|
|
; BE-PAIRED-NEXT: stxv v3, 16(r4)
|
|
; BE-PAIRED-NEXT: blr
|
|
;
|
|
; LE-PWR9-LABEL: testXLdStPair:
|
|
; LE-PWR9: # %bb.0: # %entry
|
|
; LE-PWR9-NEXT: addis r5, r2, g@toc@ha
|
|
; LE-PWR9-NEXT: sldi r3, r3, 5
|
|
; LE-PWR9-NEXT: sldi r4, r4, 5
|
|
; LE-PWR9-NEXT: addi r5, r5, g@toc@l
|
|
; LE-PWR9-NEXT: add r6, r5, r3
|
|
; LE-PWR9-NEXT: lxvx vs1, r5, r3
|
|
; LE-PWR9-NEXT: lxv vs0, 16(r6)
|
|
; LE-PWR9-NEXT: add r6, r5, r4
|
|
; LE-PWR9-NEXT: stxvx vs1, r5, r4
|
|
; LE-PWR9-NEXT: stxv vs0, 16(r6)
|
|
; LE-PWR9-NEXT: blr
|
|
;
|
|
; LE-PWR8-LABEL: testXLdStPair:
|
|
; LE-PWR8: # %bb.0: # %entry
|
|
; LE-PWR8-NEXT: addis r5, r2, g@toc@ha
|
|
; LE-PWR8-NEXT: sldi r3, r3, 5
|
|
; LE-PWR8-NEXT: li r7, 16
|
|
; LE-PWR8-NEXT: addi r5, r5, g@toc@l
|
|
; LE-PWR8-NEXT: add r6, r5, r3
|
|
; LE-PWR8-NEXT: lxvd2x vs1, r5, r3
|
|
; LE-PWR8-NEXT: sldi r3, r4, 5
|
|
; LE-PWR8-NEXT: lxvd2x vs0, r6, r7
|
|
; LE-PWR8-NEXT: add r4, r5, r3
|
|
; LE-PWR8-NEXT: stxvd2x vs1, r5, r3
|
|
; LE-PWR8-NEXT: stxvd2x vs0, r4, r7
|
|
; LE-PWR8-NEXT: blr
|
|
;
|
|
; BE-PWR9-LABEL: testXLdStPair:
|
|
; BE-PWR9: # %bb.0: # %entry
|
|
; BE-PWR9-NEXT: addis r5, r2, g@toc@ha
|
|
; BE-PWR9-NEXT: sldi r3, r3, 5
|
|
; BE-PWR9-NEXT: sldi r4, r4, 5
|
|
; BE-PWR9-NEXT: addi r5, r5, g@toc@l
|
|
; BE-PWR9-NEXT: add r6, r5, r3
|
|
; BE-PWR9-NEXT: lxvx vs1, r5, r3
|
|
; BE-PWR9-NEXT: lxv vs0, 16(r6)
|
|
; BE-PWR9-NEXT: add r6, r5, r4
|
|
; BE-PWR9-NEXT: stxvx vs1, r5, r4
|
|
; BE-PWR9-NEXT: stxv vs0, 16(r6)
|
|
; BE-PWR9-NEXT: blr
|
|
;
|
|
; BE-PWR8-LABEL: testXLdStPair:
|
|
; BE-PWR8: # %bb.0: # %entry
|
|
; BE-PWR8-NEXT: addis r5, r2, g@toc@ha
|
|
; BE-PWR8-NEXT: sldi r3, r3, 5
|
|
; BE-PWR8-NEXT: sldi r4, r4, 5
|
|
; BE-PWR8-NEXT: addi r5, r5, g@toc@l
|
|
; BE-PWR8-NEXT: add r6, r5, r3
|
|
; BE-PWR8-NEXT: lxvd2x vs0, r5, r3
|
|
; BE-PWR8-NEXT: li r3, 16
|
|
; BE-PWR8-NEXT: lxvd2x vs1, r6, r3
|
|
; BE-PWR8-NEXT: add r6, r5, r4
|
|
; BE-PWR8-NEXT: stxvd2x vs0, r5, r4
|
|
; BE-PWR8-NEXT: stxvd2x vs1, r6, r3
|
|
; BE-PWR8-NEXT: blr
|
|
entry:
|
|
%arrayidx = getelementptr inbounds <256 x i1>, ptr @g, i64 %SrcIdx
|
|
%0 = load <256 x i1>, ptr %arrayidx, align 64
|
|
%arrayidx1 = getelementptr inbounds <256 x i1>, ptr @g, i64 %DstIdx
|
|
store <256 x i1> %0, ptr %arrayidx1, align 64
|
|
ret void
|
|
}
|
|
|
|
define dso_local void @testUnalignedLdStPair() {
|
|
; LE-PAIRED-LABEL: testUnalignedLdStPair:
|
|
; LE-PAIRED: # %bb.0: # %entry
|
|
; LE-PAIRED-NEXT: plxv v3, g@PCREL+11(0), 1
|
|
; LE-PAIRED-NEXT: plxv vs0, g@PCREL+27(0), 1
|
|
; LE-PAIRED-NEXT: pstxv vs0, g@PCREL+35(0), 1
|
|
; LE-PAIRED-NEXT: pstxv v3, g@PCREL+19(0), 1
|
|
; LE-PAIRED-NEXT: blr
|
|
;
|
|
; BE-PAIRED-LABEL: testUnalignedLdStPair:
|
|
; BE-PAIRED: # %bb.0: # %entry
|
|
; BE-PAIRED-NEXT: addis r3, r2, g@toc@ha
|
|
; BE-PAIRED-NEXT: addi r3, r3, g@toc@l
|
|
; BE-PAIRED-NEXT: plxv v3, 27(r3), 0
|
|
; BE-PAIRED-NEXT: plxv vs0, 11(r3), 0
|
|
; BE-PAIRED-NEXT: pstxv v3, 35(r3), 0
|
|
; BE-PAIRED-NEXT: pstxv vs0, 19(r3), 0
|
|
; BE-PAIRED-NEXT: blr
|
|
;
|
|
; LE-PWR9-LABEL: testUnalignedLdStPair:
|
|
; LE-PWR9: # %bb.0: # %entry
|
|
; LE-PWR9-NEXT: addis r3, r2, g@toc@ha
|
|
; LE-PWR9-NEXT: li r4, 11
|
|
; LE-PWR9-NEXT: addi r3, r3, g@toc@l
|
|
; LE-PWR9-NEXT: lxvx vs0, r3, r4
|
|
; LE-PWR9-NEXT: li r4, 27
|
|
; LE-PWR9-NEXT: lxvx vs1, r3, r4
|
|
; LE-PWR9-NEXT: li r4, 35
|
|
; LE-PWR9-NEXT: stxvx vs1, r3, r4
|
|
; LE-PWR9-NEXT: li r4, 19
|
|
; LE-PWR9-NEXT: stxvx vs0, r3, r4
|
|
; LE-PWR9-NEXT: blr
|
|
;
|
|
; LE-PWR8-LABEL: testUnalignedLdStPair:
|
|
; LE-PWR8: # %bb.0: # %entry
|
|
; LE-PWR8-NEXT: addis r3, r2, g@toc@ha
|
|
; LE-PWR8-NEXT: li r4, 11
|
|
; LE-PWR8-NEXT: addi r3, r3, g@toc@l
|
|
; LE-PWR8-NEXT: lxvd2x vs0, r3, r4
|
|
; LE-PWR8-NEXT: li r4, 27
|
|
; LE-PWR8-NEXT: lxvd2x vs1, r3, r4
|
|
; LE-PWR8-NEXT: li r4, 35
|
|
; LE-PWR8-NEXT: stxvd2x vs1, r3, r4
|
|
; LE-PWR8-NEXT: li r4, 19
|
|
; LE-PWR8-NEXT: stxvd2x vs0, r3, r4
|
|
; LE-PWR8-NEXT: blr
|
|
;
|
|
; BE-PWR9-LABEL: testUnalignedLdStPair:
|
|
; BE-PWR9: # %bb.0: # %entry
|
|
; BE-PWR9-NEXT: addis r3, r2, g@toc@ha
|
|
; BE-PWR9-NEXT: li r4, 11
|
|
; BE-PWR9-NEXT: addi r3, r3, g@toc@l
|
|
; BE-PWR9-NEXT: lxvx vs0, r3, r4
|
|
; BE-PWR9-NEXT: li r4, 27
|
|
; BE-PWR9-NEXT: lxvx vs1, r3, r4
|
|
; BE-PWR9-NEXT: li r4, 35
|
|
; BE-PWR9-NEXT: stxvx vs1, r3, r4
|
|
; BE-PWR9-NEXT: li r4, 19
|
|
; BE-PWR9-NEXT: stxvx vs0, r3, r4
|
|
; BE-PWR9-NEXT: blr
|
|
;
|
|
; BE-PWR8-LABEL: testUnalignedLdStPair:
|
|
; BE-PWR8: # %bb.0: # %entry
|
|
; BE-PWR8-NEXT: addis r3, r2, g@toc@ha
|
|
; BE-PWR8-NEXT: li r4, 11
|
|
; BE-PWR8-NEXT: addi r3, r3, g@toc@l
|
|
; BE-PWR8-NEXT: lxvd2x vs0, r3, r4
|
|
; BE-PWR8-NEXT: li r4, 27
|
|
; BE-PWR8-NEXT: lxvd2x vs1, r3, r4
|
|
; BE-PWR8-NEXT: li r4, 35
|
|
; BE-PWR8-NEXT: stxvd2x vs1, r3, r4
|
|
; BE-PWR8-NEXT: li r4, 19
|
|
; BE-PWR8-NEXT: stxvd2x vs0, r3, r4
|
|
; BE-PWR8-NEXT: blr
|
|
entry:
|
|
%add.ptr = getelementptr inbounds i8, ptr @g, i64 11
|
|
%add.ptr1 = getelementptr inbounds i8, ptr @g, i64 19
|
|
%0 = load <256 x i1>, ptr %add.ptr, align 64
|
|
store <256 x i1> %0, ptr %add.ptr1, align 64
|
|
ret void
|
|
}
|