llvm-project/GlobalISel at 7d8da04c26bffd9da4461eef181df39c46292fa3 - llvm-project - shylie's gitea

shylie/llvm-project

History

Alex Bradbury dd662d8028

[RISCV] Handle ADD in RISCVInstrInfo::isCopyInstrImpl (#81123 )

Split out from #77610 and features a test, as a buggy version of this
caused a regression when landing that patch (the previous version had a
typo picking the wrong register as the source).

This is also motivated by future changes to MachineCopyPropagation which will use this information to determine if we have been left with a nop mv.

2025-03-05 12:29:04 +00:00

..

instruction-select

[RISCV] Select mask operands as virtual registers and eliminate uses of vmv0 (#125026 )

2025-02-12 12:06:55 +08:00

[RISCV][GISel] Fallback in LowerCall for byval arguments. (#119251 )

2024-12-09 14:22:05 -08:00

[AArch64][GlobalISel] Add disjoint handling for add_and_or_is_add. (#123594 )

2025-02-02 21:01:49 +00:00

[RISCV][GISel] Remove -disable-gisel-legality-check from most RVV tests. NFC

2024-11-15 12:04:55 -08:00

[RISCV][GISEL] instruction-select vmclr (#110782 )

2024-10-04 12:51:04 -04:00

add-imm.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

alu-roundtrip-rv64.ll

…

alu-roundtrip.ll

[RISCV] GISel custom lowering for G_ADD/G_SUB (#121587 )

2025-01-07 18:53:10 -08:00

atomic-fence.ll

…

atomic-load-store.ll

[RISCV][GISel] Add atomic load/store test. Add additional atomic load/store isel patterns."

2024-11-20 22:23:18 -08:00

bitmanip.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445 )

2024-11-15 17:53:14 +08:00

calllowering-ret.ll

…

combine-neg-abs.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

combine.ll

[RISCV] Porting hasAllNBitUsers to RISCV GISel for instruction select (#125795 )

2025-02-06 11:57:52 -05:00

combine.mir

…

constantpool.ll

…

constbarrier-rv32.ll

[RISCV] Handle ADD in RISCVInstrInfo::isCopyInstrImpl (#81123 )

2025-03-05 12:29:04 +00:00

constbarrier-rv64.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445 )

2024-11-15 17:53:14 +08:00

div-by-constant.ll

[RISCV] Porting hasAllNBitUsers to RISCV GISel for instruction select (#125795 )

2025-02-06 11:57:52 -05:00

double-arith.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

double-convert.ll

[GISel][RISCV] Use isSExtCheaperThanZExt when widening G_ICMP. (#120032 )

2024-12-15 22:55:58 -08:00

double-fcmp.ll

[GISel][RISCV] Use isSExtCheaperThanZExt when widening G_ICMP. (#120032 )

2024-12-15 22:55:58 -08:00

double-intrinsics.ll

[RISCV][GISel] Added GISelPredicateCodes to LeadingOnes*Mask (#119886 )

2024-12-13 14:23:16 -08:00

double-zfa.ll

[RISCV][GISel] Support G_MERGE_VALUES/G_UNMERGE_VALUES with Zfa. (#120379 )

2025-01-07 07:50:50 -08:00

float-arith.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

float-convert.ll

[GISel][RISCV] Use isSExtCheaperThanZExt when widening G_ICMP. (#120032 )

2024-12-15 22:55:58 -08:00

float-fclass.ll

[RISCV][GISel] Add FCLASS to onlyUsesFP for register bank selection (#118021 )

2024-12-02 11:19:08 -08:00

float-fcmp.ll

[GISel][RISCV] Use isSExtCheaperThanZExt when widening G_ICMP. (#120032 )

2024-12-15 22:55:58 -08:00

float-intrinsics.ll

[GISel][RISCV] Use isSExtCheaperThanZExt when widening G_ICMP. (#120032 )

2024-12-15 22:55:58 -08:00

float-zfa.ll

[RISCV][GISel] Add Zfa FP legalization and full tests for 9 insn (#118723 )

2024-12-05 12:49:07 -08:00

fp128.ll

[RISCV][GISel] Add legalization for more fp128 libcalls.

2024-12-16 23:39:09 -08:00

fpr-gpr-copy-rv32.ll

…

fpr-gpr-copy-rv64.ll

…

freeze.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

gisel-commandline-option.ll

Revert "[RISCV][GISEL] Introduce the RISCVPostLegalizerLowering pass (#108991 )"

2024-09-20 07:01:17 -07:00

half-zfa.ll

[RISCV][GISel] Add Zfa FP legalization and full tests for 9 insn (#118723 )

2024-12-05 12:49:07 -08:00

iabs.ll

[RISCV] GISel custom lowering for G_ADD/G_SUB (#121587 )

2025-01-07 18:53:10 -08:00

irtranslator-calllowering.ll

…

jumptable.ll

[RISCV][GISel] Move G_BRJT expansion to legalization (#73711 )

2024-11-20 13:43:36 -08:00

knownbits-copy-crash.mir

[GISel] Teach computeKnownBitsImpl to handle COPY instructions that change bit width. (#118924 )

2024-12-06 21:31:19 -08:00

legalizer-info-validation.mir

[RISCV] GISel custom lowering for G_ADD/G_SUB (#121587 )

2025-01-07 18:53:10 -08:00

libcalls.ll

…

phi.ll

[RISCV][GISel] Allow s32 G_PHI for RV64 to support f32 phis.

2024-12-06 11:53:57 -08:00

riscv-unsupported.ll

[RISCV][GISel] Fallback in LowerCall for byval arguments. (#119251 )

2024-12-09 14:22:05 -08:00

rotl-rotr.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

rv32zba.ll

[RISCV][GISel] Copy some Zba IR test cases from SelectionDAG. NFC

2024-11-14 13:47:49 -08:00

rv32zbb-zbkb.ll

[RISCV][GISel] Port TrailingOnesMask PatLeaf. (#119427 )

2024-12-10 22:17:52 -08:00

rv32zbb.ll

[RISCV][GISel] Port TrailingOnesMask PatLeaf. (#119427 )

2024-12-10 22:17:52 -08:00

rv32zbkb.ll

[RISCV][GISel] Port TrailingOnesMask PatLeaf. (#119427 )

2024-12-10 22:17:52 -08:00

rv64-double-convert.ll

[RISCV][GISel] Improve fptos/ui and s/uitofp handling and testing.

2024-11-06 12:18:56 -08:00

rv64-float-convert.ll

[RISCV][GISel] Improve fptos/ui and s/uitofp handling and testing.

2024-11-06 12:18:56 -08:00

rv64zba.ll

[RISCV][GISel] Added GISelPredicateCodes to LeadingOnes*Mask (#119886 )

2024-12-13 14:23:16 -08:00

rv64zbb-zbkb.ll

[RISCV] Porting hasAllNBitUsers to RISCV GISel for instruction select (#125795 )

2025-02-06 11:57:52 -05:00

rv64zbb.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

rv64zbkb.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

scalablevec-combiner-crash.ll

[GlobalISel] Add bail outs for scalable vectors to some combines. (#106496 )

2024-08-29 14:02:53 -07:00

scmp.ll

[RISCV] GISel custom lowering for G_ADD/G_SUB (#121587 )

2025-01-07 18:53:10 -08:00

shift.ll

[RISCV][GISel] Custom promote s32 G_SHL/ASHR/LSHR on RV64. (#115559 )

2024-11-11 20:59:21 -08:00

shifts.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

stacksave-stackrestore.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

ucmp.ll

[RISCV] GISel custom lowering for G_ADD/G_SUB (#121587 )

2025-01-07 18:53:10 -08:00

vararg.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

wide-scalar-shift-by-byte-multiple-legalization.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00