llvm-project

65704-illegal-instruction.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445 )

2024-11-15 17:53:14 +08:00

abd.ll

[RISCV] Enable RVV ABD tests with i64 elements (#124246 )

2025-02-05 14:51:47 +08:00

abs-sdnode.ll

…

abs-vp.ll

[RISCV] Clear vill for whole vector register moves in vsetvli insertion (#118283 )

2024-12-06 00:48:05 +08:00

access-fixed-objects-by-rvv.ll

[RISCV] Add stack clash vector support (#119458 )

2025-01-10 09:48:21 -08:00

active_lane_mask.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

addi-rvv-stack-object.mir

[llvm] Mark scavenging spill-slots as *spilled* stack objects. (#122673 )

2025-01-14 10:18:31 +02:00

addi-scalable-offset.mir

[RISC-V] Fix incorrect epilogue_begin setting in debug line table (#120623 )

2025-01-28 21:03:12 +05:30

aliases.mir

…

alloca-load-store-scalable-array.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

alloca-load-store-scalable-struct.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

alloca-load-store-vector-tuple.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445 )

2024-11-15 17:53:14 +08:00

allocate-lmul-2-4-8.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445 )

2024-11-15 17:53:14 +08:00

allone-masked-to-unmasked.ll

…

allone-masked-to-unmasked.mir

[RISCV] Fix masked->unmasked peephole handling masked pseudos with no passthru (#122253 )

2025-01-09 19:54:37 +08:00

binop-splats.ll

[RISCV][CFI] add function epilogue cfi information (#110810 )

2024-11-06 00:20:21 +03:00

binop-zext.ll

[RISCV] Combine ({s,u}{div,rem} (zext, zext)) -> (zext ({s,u}{div,rem} (zext, zext))) (#86779 )

2024-03-29 05:55:38 +08:00

bitreverse-sdnode.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

bitreverse-vp.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

bswap-sdnode.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

bswap-vp.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

callee-saved-regs.ll

[RISCV][CFI] add function epilogue cfi information (#110810 )

2024-11-06 00:20:21 +03:00

calling-conv-fastcc.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

calling-conv.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

ceil-vp.ll

[RISCV] Move VMV0 elimination past machine SSA opts (#126850 )

2025-02-20 12:41:05 +08:00

cmp-folds.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

combine-ctpop-to-vcpop.ll

[RISCV] Add DAG combine to convert (iX ctpop (bitcast (vXi1 A))) into vcpop.m. (#117062 )

2024-11-21 11:12:07 -08:00

combine-reduce-add-to-vcpop.ll

[RISCV] Adjust RISCVVectorMaskDAGMutation to look for copy to V0 (#129296 )

2025-03-05 08:56:09 -08:00

combine-sats.ll

[RISCV] Convert more constant splats in tests to splat shorthand. NFC (#87616 )

2024-04-09 15:46:38 +08:00

combine-splats.ll

[RISCV] Convert more constant splats in tests to splat shorthand. NFC (#87616 )

2024-04-09 15:46:38 +08:00

combine-store-extract-crash.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

combine-store.ll

[RISCV] Enable store clustering by default (#73796 )

2024-10-11 20:25:53 +01:00

common-shuffle-patterns.ll

[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404 )

2023-09-06 10:43:41 +01:00

commutable.ll

[RISCV] Move VMV0 elimination past machine SSA opts (#126850 )

2025-02-20 12:41:05 +08:00

commuted-op-indices-regression.mir

[test] -march -> -mtriple (#67741 )

2023-09-29 10:43:23 -07:00

compressstore.ll

[RISCV] Clear vill for whole vector register moves in vsetvli insertion (#118283 )

2024-12-06 00:48:05 +08:00

concat-vector-insert-elt.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

concat-vectors-constant-stride.ll

[RISCV] Move RISCVInsertVSETVLI to after phi elimination (#91440 )

2024-05-15 11:44:32 +08:00

constant-folding-crash.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

constant-folding.ll

[RISCV] Convert more constant splats in tests to splat shorthand. NFC (#87616 )

2024-04-09 15:46:38 +08:00

copyprop.mir

[RISCV] Move VMV0 elimination past machine SSA opts (#126850 )

2025-02-20 12:41:05 +08:00

cross-block-cse.ll

…

ctlz-sdnode.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

ctlz-vp.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

ctpop-sdnode.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445 )

2024-11-15 17:53:14 +08:00

ctpop-vp.ll

[RISCV] Clear vill for whole vector register moves in vsetvli insertion (#118283 )

2024-12-06 00:48:05 +08:00

cttz-sdnode.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

cttz-vp.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

debug-info-rvv-dbg-value.mir

[test] Change llc -march= to -mtriple=

2023-09-11 14:42:37 -07:00

dont-sink-splat-operands.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

double-round-conv.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

emergency-slot.mir

[RISC-V] Fix incorrect epilogue_begin setting in debug line table (#120623 )

2025-01-28 21:03:12 +05:30

expand-no-v.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445 )

2024-11-15 17:53:14 +08:00

expandload.ll

[RISCV] Delete dead COPYs to vmv0 during vmv0 elimination

2025-02-26 23:09:50 +08:00

extload-truncstore.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

extract-subvector.ll

[RISCV] Clear vill for whole vector register moves in vsetvli insertion (#118283 )

2024-12-06 00:48:05 +08:00

extractelt-fp.ll

[DAG] shouldReduceLoadWidth - hasOneUse should check just the loaded value - not the chain (#128167 )

2025-02-24 11:09:41 +00:00

extractelt-i1.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

extractelt-int-rv32.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445 )

2024-11-15 17:53:14 +08:00

extractelt-int-rv64.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fceil-constrained-sdnode.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fceil-sdnode.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

ffloor-constrained-sdnode.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

ffloor-sdnode.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-neg-abs.ll

[DAGCombiner] Turn (neg (max x, (neg x))) into (min x, (neg x)) (#120666 )

2025-01-02 16:28:55 -08:00

fixed-vector-i8-index-cornercase.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-abd.ll

[RISCV] Enable sub(max, min) lowering for ABDS and ABDU (#86592 )

2024-03-25 20:13:53 -07:00

fixed-vectors-abs-vp.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-abs.ll

[RISCV][VLOPT] Enable the RISCVVLOptimizer by default (#119461 )

2024-12-17 16:19:35 -05:00

fixed-vectors-binop-splats.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445 )

2024-11-15 17:53:14 +08:00

fixed-vectors-bitcast-large-vector.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-bitcast.ll

[RISCV][CFI] add function epilogue cfi information (#110810 )

2024-11-06 00:20:21 +03:00

fixed-vectors-bitreverse-vp.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-bitreverse.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445 )

2024-11-15 17:53:14 +08:00

fixed-vectors-bswap-vp.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-bswap.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445 )

2024-11-15 17:53:14 +08:00

fixed-vectors-buildvec-of-binop.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-calling-conv-fastcc.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-calling-conv.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-ceil-vp.ll

[RISCV] Delete dead COPYs to vmv0 during vmv0 elimination

2025-02-26 23:09:50 +08:00

fixed-vectors-compress-fp.ll

[RISCV] Lower @llvm.experimental.vector.compress for zvfhmin/zvfbfmin (#113770 )

2024-10-28 09:37:06 +00:00

fixed-vectors-compress-int.ll

[RISCV] Add lowering for @llvm.experimental.vector.compress (#113291 )

2024-10-23 14:22:32 +08:00

fixed-vectors-compressstore-fp.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

fixed-vectors-compressstore-int.ll

[RISCV] Support llvm.masked.compressstore intrinsic (#83457 )

2024-03-13 15:18:51 -04:00

fixed-vectors-ctlz-vp.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-ctlz.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445 )

2024-11-15 17:53:14 +08:00

fixed-vectors-ctpop-vp.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-ctpop.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-cttz-vp.ll

[RISCV] Delete dead COPYs to vmv0 during vmv0 elimination

2025-02-26 23:09:50 +08:00

fixed-vectors-cttz.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-deinterleave-load.ll

[RISCV] Recognize de-interleave shuffles with 2 sources. (#127272 )

2025-02-16 20:40:09 -08:00

fixed-vectors-elen.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-emergency-slot.mir

[CodeGen] Convert tests to opaque pointers (NFC)

2024-02-05 14:07:09 +01:00

fixed-vectors-expandload-fp.ll

[RISCV] Support llvm.masked.expandload intrinsic (#101954 )

2024-10-31 20:03:58 +08:00

fixed-vectors-expandload-int.ll

[RISCV] Support llvm.masked.expandload intrinsic (#101954 )

2024-10-31 20:03:58 +08:00

fixed-vectors-extload-truncstore.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-extract-i1.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-extract-subvector.ll

[DAG] shouldReduceLoadWidth - hasOneUse should check just the loaded value - not the chain (#128167 )

2025-02-24 11:09:41 +00:00

fixed-vectors-extract.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-fceil-constrained-sdnode.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-ffloor-constrained-sdnode.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-floor-vp.ll

[RISCV] Delete dead COPYs to vmv0 during vmv0 elimination

2025-02-26 23:09:50 +08:00

fixed-vectors-fmaximum-vp.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-fmaximum.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-fmf.ll

[RISCV] Split widening floating point fused multiple-add pseudo instructions by SEW

2024-04-12 07:06:40 -07:00

fixed-vectors-fminimum-vp.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-fminimum.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-fnearbyint-constrained-sdnode.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-fp2i-sat.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

fixed-vectors-fp2i.ll

[RISCV] Optimize (slli (srli (slli X, C1), C1), C2) -> (srli (slli X, C1), C1-C2) (#119567 )

2024-12-12 07:58:36 +01:00

fixed-vectors-fp-bitcast.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

fixed-vectors-fp-buildvec-bf16.ll

[RISCV] Lower fixed-length {insert,extract}_vector_elt on zvfhmin/zvfbfmin (#114927 )

2024-11-05 13:57:59 +08:00

fixed-vectors-fp-buildvec.ll

[RISCV] Adjust RISCVVectorMaskDAGMutation to look for copy to V0 (#129296 )

2025-03-05 08:56:09 -08:00

fixed-vectors-fp-conv.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

fixed-vectors-fp-interleave.ll

[RISCV] Recognize VLA shift pairs from shuffle masks (#127710 )

2025-02-20 07:50:49 -08:00

fixed-vectors-fp-setcc.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-fp-shuffles.ll

[RISCV] Recognize VLA shift pairs from shuffle masks (#127710 )

2025-02-20 07:50:49 -08:00

fixed-vectors-fp-splat-bf16.ll

[RISCV] Bitcast fixed length bf16/f16 build_vector to i16 with Zvfbfmin/Zvfhmin+Zfbfmin/Zfhmin. (#106637 )

2024-09-03 17:50:04 -07:00

fixed-vectors-fp-splat.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

fixed-vectors-fp-vrgather.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-fp.ll

[RISCV] Move VMV0 elimination past machine SSA opts (#126850 )

2025-02-20 12:41:05 +08:00

fixed-vectors-fpext-vp.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-fpowi.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-fptosi-vp-mask.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

fixed-vectors-fptosi-vp.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-fptoui-vp-mask.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

fixed-vectors-fptoui-vp.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-fptrunc-vp.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-fround-constrained-sdnode.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-fround.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-froundeven-constrained-sdnode.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-froundeven.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-fshr-fshl-vp.ll

[RISCV] Clear vill for whole vector register moves in vsetvli insertion (#118283 )

2024-12-06 00:48:05 +08:00

fixed-vectors-ftrunc-constrained-sdnode.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445 )

2024-11-15 17:53:14 +08:00

fixed-vectors-i2fp.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

fixed-vectors-insert-i1.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445 )

2024-11-15 17:53:14 +08:00

fixed-vectors-insert-subvector-shuffle.ll

[RISCV][VLOPT] Add support for VID and VIOTA (#120331 )

2024-12-17 21:15:23 -05:00

fixed-vectors-insert-subvector.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-insert.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-int-buildvec.ll

[RISCV] Adjust RISCVVectorMaskDAGMutation to look for copy to V0 (#129296 )

2025-03-05 08:56:09 -08:00

fixed-vectors-int-explodevector.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445 )

2024-11-15 17:53:14 +08:00

fixed-vectors-int-exttrunc.ll

[RISCV] Remove -riscv-v-fixed-length-vector-lmul-max from tests. NFC (#78299 )

2024-02-14 16:12:37 +08:00

fixed-vectors-int-interleave.ll

[RISCV] Recognize VLA shift pairs from shuffle masks (#127710 )

2025-02-20 07:50:49 -08:00

fixed-vectors-int-setcc.ll

[RISCV] Convert more constant splats in tests to splat shorthand. NFC (#87616 )

2024-04-09 15:46:38 +08:00

fixed-vectors-int-shuffles.ll

[RISCV] Adjust RISCVVectorMaskDAGMutation to look for copy to V0 (#129296 )

2025-03-05 08:56:09 -08:00

fixed-vectors-int-splat.ll

[RISCV][CFI] add function epilogue cfi information (#110810 )

2024-11-06 00:20:21 +03:00

fixed-vectors-int-vrgather.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-int.ll

[RISCV] Adjust RISCVVectorMaskDAGMutation to look for copy to V0 (#129296 )

2025-03-05 08:56:09 -08:00

fixed-vectors-interleave-store.ll

[IA] Generalize the support for power-of-two (de)interleave intrinsics (#123863 )

2025-01-23 15:27:51 -08:00

fixed-vectors-interleaved-access-zve32x.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-interleaved-access.ll

[RISCV] Adjust RISCVVectorMaskDAGMutation to look for copy to V0 (#129296 )

2025-03-05 08:56:09 -08:00

fixed-vectors-inttoptr-ptrtoint.ll

[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404 )

2023-09-06 10:43:41 +01:00

fixed-vectors-llrint-vp.ll

[VP][RISCV] Introduce vp.lrint/llrint and RISC-V support. (#82627 )

2024-02-26 16:37:41 +08:00

fixed-vectors-llrint.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-load-store.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

fixed-vectors-load.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445 )

2024-11-15 17:53:14 +08:00

fixed-vectors-lrint-vp.ll

[RISCV] Fix missing CHECK prefixes in vector lrint test files. NFC

2024-04-08 16:01:18 -07:00

fixed-vectors-lrint.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-marith-vp.ll

[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404 )

2023-09-06 10:43:41 +01:00

fixed-vectors-mask-buildvec.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-mask-load-store.ll

[RISCV] Remove -riscv-v-fixed-length-vector-lmul-max from tests. NFC (#78299 )

2024-02-14 16:12:37 +08:00

fixed-vectors-mask-logic.ll

[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404 )

2023-09-06 10:43:41 +01:00

fixed-vectors-mask-splat.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-masked-gather.ll

[RISCV] Adjust RISCVVectorMaskDAGMutation to look for copy to V0 (#129296 )

2025-03-05 08:56:09 -08:00

fixed-vectors-masked-load-fp.ll

[RISCV] Adjust RISCVVectorMaskDAGMutation to look for copy to V0 (#129296 )

2025-03-05 08:56:09 -08:00

fixed-vectors-masked-load-int.ll

[RISCV] Adjust RISCVVectorMaskDAGMutation to look for copy to V0 (#129296 )

2025-03-05 08:56:09 -08:00

fixed-vectors-masked-scatter.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-masked-store-fp.ll

[RISCV] Adjust RISCVVectorMaskDAGMutation to look for copy to V0 (#129296 )

2025-03-05 08:56:09 -08:00

fixed-vectors-masked-store-int.ll

[RISCV] Adjust RISCVVectorMaskDAGMutation to look for copy to V0 (#129296 )

2025-03-05 08:56:09 -08:00

fixed-vectors-nearbyint-vp.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-non-power-of-2.ll

[RISCV] Introduce local peephole to reduce VLs based on demanded VL (#104689 )

2024-08-22 07:34:41 -07:00

fixed-vectors-peephole-vmerge-vops.ll

[RISCV] Convert more constant splats in tests to splat shorthand. NFC (#87616 )

2024-04-09 15:46:38 +08:00

fixed-vectors-reduction-formation.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-reduction-fp-vp.ll

[RISCV] The test for vp.reduce.fminimum/fmaximum with fixed-length should stay in fixed-vectors-reduction-fp-vp.ll. (NFC)

2025-02-26 10:32:57 +08:00

fixed-vectors-reduction-fp.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-reduction-int-vp.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-reduction-int.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-reduction-mask-vp.ll

[RISCV] Clear vill for whole vector register moves in vsetvli insertion (#118283 )

2024-12-06 00:48:05 +08:00

fixed-vectors-rint-vp.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-round-vp.ll

[RISCV] Delete dead COPYs to vmv0 during vmv0 elimination

2025-02-26 23:09:50 +08:00

fixed-vectors-roundeven-vp.ll

[RISCV] Delete dead COPYs to vmv0 during vmv0 elimination

2025-02-26 23:09:50 +08:00

fixed-vectors-roundtozero-vp.ll

[RISCV] Delete dead COPYs to vmv0 during vmv0 elimination

2025-02-26 23:09:50 +08:00

fixed-vectors-sad.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445 )

2024-11-15 17:53:14 +08:00

fixed-vectors-scalarized.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445 )

2024-11-15 17:53:14 +08:00

fixed-vectors-segN-load.ll

[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404 )

2023-09-06 10:43:41 +01:00

fixed-vectors-segN-store.ll

…

fixed-vectors-select-addsub.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-select-bf16.ll

[RISCV] Remove experimental for bf16 extensions (#97996 )

2024-07-09 14:34:03 +08:00

fixed-vectors-select-fp.ll

[RISCV] Add back some test cases I inadvertently deleted. NFC

2024-06-24 10:01:52 -07:00

fixed-vectors-select-int.ll

[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404 )

2023-09-06 10:43:41 +01:00

fixed-vectors-setcc-fp-vp.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-setcc-int-vp-mask.ll

[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404 )

2023-09-06 10:43:41 +01:00

fixed-vectors-setcc-int-vp.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-sext-vp-mask.ll

[RISCV] Convert more constant splats in tests to splat shorthand. NFC (#87616 )

2024-04-09 15:46:38 +08:00

fixed-vectors-sext-vp.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-shuffle-changes-length.ll

[RISCV] Adjust RISCVVectorMaskDAGMutation to look for copy to V0 (#129296 )

2025-03-05 08:56:09 -08:00

fixed-vectors-shuffle-concat.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-shuffle-deinterleave.ll

[RISCV] Adjust RISCVVectorMaskDAGMutation to look for copy to V0 (#129296 )

2025-03-05 08:56:09 -08:00

fixed-vectors-shuffle-exact-vlen.ll

[RISCV] Adjust RISCVVectorMaskDAGMutation to look for copy to V0 (#129296 )

2025-03-05 08:56:09 -08:00

fixed-vectors-shuffle-extract-subvector.ll

[RISCV] Remove unncessary FP extensions from some integer only vector tests.

2024-07-31 15:21:03 -07:00

fixed-vectors-shuffle-reverse.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-shuffle-rotate.ll

[RISCV] Recognize VLA shift pairs from shuffle masks (#127710 )

2025-02-20 07:50:49 -08:00

fixed-vectors-shuffle-transpose.ll

[RISCV] Recognize VLA shift pairs from shuffle masks (#127710 )

2025-02-20 07:50:49 -08:00

fixed-vectors-shuffle-vslide1down.ll

[RISCV][CFI] add function epilogue cfi information (#110810 )

2024-11-06 00:20:21 +03:00

fixed-vectors-shuffle-vslide1up.ll

[RISCV] Recognize VLA shift pairs from shuffle masks (#127710 )

2025-02-20 07:50:49 -08:00

fixed-vectors-shufflevector-vnsrl.ll

[RISCV] Adjust RISCVVectorMaskDAGMutation to look for copy to V0 (#129296 )

2025-03-05 08:56:09 -08:00

fixed-vectors-sitofp-vp-mask.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

fixed-vectors-sitofp-vp.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-stepvector.ll

Move stepvector intrinsic out of experimental namespace (#98043 )

2024-08-28 12:48:20 +01:00

fixed-vectors-store-merge-crash.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-store.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445 )

2024-11-15 17:53:14 +08:00

fixed-vectors-strided-load-combine.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445 )

2024-11-15 17:53:14 +08:00

fixed-vectors-strided-load-store-asm.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-strided-load-store-negative.ll

[LLVM][IR] Use splat syntax when printing Constant[Data]Vector. (#112548 )

2024-11-06 11:53:33 +00:00

fixed-vectors-strided-load-store.ll

[RISCV] Allow non-loop invariant steps in RISCVGatherScatterLowering (#122244 )

2025-01-17 08:58:56 +08:00

fixed-vectors-strided-vpload.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-strided-vpstore.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-trunc-sat-clip.ll

[RISCV] Don't support TRUNCATE_SSAT_U. (#104468 )

2024-08-16 08:42:36 -07:00

fixed-vectors-trunc-vp-mask.ll

[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404 )

2023-09-06 10:43:41 +01:00

fixed-vectors-trunc-vp.ll

[RISCV] Delete dead COPYs to vmv0 during vmv0 elimination

2025-02-26 23:09:50 +08:00

fixed-vectors-uitofp-vp-mask.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

fixed-vectors-uitofp-vp.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-unaligned.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-vaaddu.ll

[RISCV][CFI] add function epilogue cfi information (#110810 )

2024-11-06 00:20:21 +03:00

fixed-vectors-vadd-vp-mask.ll

[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404 )

2023-09-06 10:43:41 +01:00

fixed-vectors-vadd-vp.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-vand-vp.ll

[RISCV][CFI] add function epilogue cfi information (#110810 )

2024-11-06 00:20:21 +03:00

fixed-vectors-vcopysign-vp.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-vdiv-vp.ll

[RISCV][CFI] add function epilogue cfi information (#110810 )

2024-11-06 00:20:21 +03:00

fixed-vectors-vdivu-vp.ll

[RISCV][CFI] add function epilogue cfi information (#110810 )

2024-11-06 00:20:21 +03:00

fixed-vectors-vfabs-vp.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-vfadd-constrained-sdnode.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

fixed-vectors-vfadd-vp.ll

[LegalizeVectorOps][RISCV] Use VP_FP_EXTEND/ROUND when promoting VP_FP* operations. (#122784 )

2025-01-13 15:18:41 -08:00

fixed-vectors-vfclass-vp.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

fixed-vectors-vfclass.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

fixed-vectors-vfcmp-constrained-sdnode.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445 )

2024-11-15 17:53:14 +08:00

fixed-vectors-vfcmps-constrained-sdnode.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445 )

2024-11-15 17:53:14 +08:00

fixed-vectors-vfdiv-constrained-sdnode.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

fixed-vectors-vfdiv-vp.ll

[LegalizeVectorOps][RISCV] Use VP_FP_EXTEND/ROUND when promoting VP_FP* operations. (#122784 )

2025-01-13 15:18:41 -08:00

fixed-vectors-vfma-vp.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-vfmacc-vp.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

fixed-vectors-vfmadd-constrained-sdnode.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

fixed-vectors-vfmax-vp.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-vfmax.ll

[RISCV] Bitcast fixed length bf16/f16 build_vector to i16 with Zvfbfmin/Zvfhmin+Zfbfmin/Zfhmin. (#106637 )

2024-09-03 17:50:04 -07:00

fixed-vectors-vfmin-vp.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-vfmin.ll

[RISCV] Bitcast fixed length bf16/f16 build_vector to i16 with Zvfbfmin/Zvfhmin+Zfbfmin/Zfhmin. (#106637 )

2024-09-03 17:50:04 -07:00

fixed-vectors-vfmsac-vp.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

fixed-vectors-vfmsub-constrained-sdnode.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

fixed-vectors-vfmul-constrained-sdnode.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

fixed-vectors-vfmul-vp.ll

[LegalizeVectorOps][RISCV] Use VP_FP_EXTEND/ROUND when promoting VP_FP* operations. (#122784 )

2025-01-13 15:18:41 -08:00

fixed-vectors-vfmuladd-vp.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-vfneg-vp.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-vfnmacc-vp.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

fixed-vectors-vfnmadd-constrained-sdnode.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

fixed-vectors-vfnmsac-vp.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

fixed-vectors-vfnmsub-constrained-sdnode.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

fixed-vectors-vfpext-constrained-sdnode.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

fixed-vectors-vfptoi-constrained-sdnode.ll

[RISCV] Custom promote f16/bf16 fp_to_(s/u)int to reduce isel patterns that emit two instructions. (#107011 )

2024-09-03 15:34:25 -07:00

fixed-vectors-vfptrunc-constrained-sdnode.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

fixed-vectors-vfrdiv-vp.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

fixed-vectors-vfrsub-vp.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

fixed-vectors-vfsqrt-constrained-sdnode.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

fixed-vectors-vfsqrt-vp.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-vfsub-constrained-sdnode.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

fixed-vectors-vfsub-vp.ll

[LegalizeVectorOps][RISCV] Use VP_FP_EXTEND/ROUND when promoting VP_FP* operations. (#122784 )

2025-01-13 15:18:41 -08:00

fixed-vectors-vfw-web-simplification.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445 )

2024-11-15 17:53:14 +08:00

fixed-vectors-vfwadd.ll

[RISCV][CFI] add function epilogue cfi information (#110810 )

2024-11-06 00:20:21 +03:00

fixed-vectors-vfwmacc.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

fixed-vectors-vfwmaccbf16.ll

[ValueTypes][RISCV] Add v1bf16 type (#111112 )

2024-10-06 22:20:51 +08:00

fixed-vectors-vfwmul.ll

[RISCV][CFI] add function epilogue cfi information (#110810 )

2024-11-06 00:20:21 +03:00

fixed-vectors-vfwsub.ll

[RISCV][CFI] add function epilogue cfi information (#110810 )

2024-11-06 00:20:21 +03:00

fixed-vectors-vitofp-constrained-sdnode.ll

[RISCV] Lower scalar_to_vector for supported FP types (#114340 )

2024-10-31 13:15:17 +08:00

fixed-vectors-vmacc-vp.ll

[RISCV][CFI] add function epilogue cfi information (#110810 )

2024-11-06 00:20:21 +03:00

fixed-vectors-vmax-vp.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-vmaxu-vp.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-vmin-vp.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-vminu-vp.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-vmul-vp-mask.ll

[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404 )

2023-09-06 10:43:41 +01:00

fixed-vectors-vmul-vp.ll

[RISCV][CFI] add function epilogue cfi information (#110810 )

2024-11-06 00:20:21 +03:00

fixed-vectors-vnmsac-vp.ll

[RISCV][CFI] add function epilogue cfi information (#110810 )

2024-11-06 00:20:21 +03:00

fixed-vectors-vnsra-vnsrl.ll

[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404 )

2023-09-06 10:43:41 +01:00

fixed-vectors-vor-vp.ll

[RISCV][CFI] add function epilogue cfi information (#110810 )

2024-11-06 00:20:21 +03:00

fixed-vectors-vp-splat.ll

[RISCV][CFI] add function epilogue cfi information (#110810 )

2024-11-06 00:20:21 +03:00

fixed-vectors-vpgather.ll

[RISCV] Adjust RISCVVectorMaskDAGMutation to look for copy to V0 (#129296 )

2025-03-05 08:56:09 -08:00

fixed-vectors-vpload.ll

[RISCV] Move VMV0 elimination past machine SSA opts (#126850 )

2025-02-20 12:41:05 +08:00

fixed-vectors-vpmerge-bf16.ll

[RISCV] Bitcast fixed length bf16/f16 build_vector to i16 with Zvfbfmin/Zvfhmin+Zfbfmin/Zfhmin. (#106637 )

2024-09-03 17:50:04 -07:00

fixed-vectors-vpmerge.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-vpscatter.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-vpstore.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-vreductions-mask.ll

[NFC] [RISCV] Add tests for llvm.vector.reduce.*

2024-12-10 10:20:21 +08:00

fixed-vectors-vrem-vp.ll

[RISCV][CFI] add function epilogue cfi information (#110810 )

2024-11-06 00:20:21 +03:00

fixed-vectors-vremu-vp.ll

[RISCV][CFI] add function epilogue cfi information (#110810 )

2024-11-06 00:20:21 +03:00

fixed-vectors-vrol.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445 )

2024-11-15 17:53:14 +08:00

fixed-vectors-vror.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445 )

2024-11-15 17:53:14 +08:00

fixed-vectors-vrsub-vp.ll

[RISCV][CFI] add function epilogue cfi information (#110810 )

2024-11-06 00:20:21 +03:00

fixed-vectors-vsadd-vp.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-vsadd.ll

[RISCV][CFI] add function epilogue cfi information (#110810 )

2024-11-06 00:20:21 +03:00

fixed-vectors-vsaddu-vp.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-vsaddu.ll

[RISCV][CFI] add function epilogue cfi information (#110810 )

2024-11-06 00:20:21 +03:00

fixed-vectors-vscale-range.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-vselect-vp-bf16.ll

[RISCV] Remove Zfbfmin from some vector test RUN lines. NFC

2024-07-31 22:25:23 -07:00

fixed-vectors-vselect-vp.ll

[RISCV] Adjust RISCVVectorMaskDAGMutation to look for copy to V0 (#129296 )

2025-03-05 08:56:09 -08:00

fixed-vectors-vselect.ll

[RISCV] Move VMV0 elimination past machine SSA opts (#126850 )

2025-02-20 12:41:05 +08:00

fixed-vectors-vshl-vp.ll

[LegalizeTypes] Use VP_AND and VP_SHL/VP_SRA to promote operands fo VP arithmetic. (#92799 )

2024-05-28 12:49:42 -07:00

fixed-vectors-vsra-vp.ll

[LegalizeTypes] Use VP_AND and VP_SHL/VP_SRA to promote operands fo VP arithmetic. (#92799 )

2024-05-28 12:49:42 -07:00

fixed-vectors-vsrl-vp.ll

[LegalizeTypes] Use VP_AND and VP_SHL/VP_SRA to promote operands fo VP arithmetic. (#92799 )

2024-05-28 12:49:42 -07:00

fixed-vectors-vssub-vp.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-vssub.ll

[RISCV][CFI] add function epilogue cfi information (#110810 )

2024-11-06 00:20:21 +03:00

fixed-vectors-vssubu-vp.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-vssubu.ll

[RISCV][CFI] add function epilogue cfi information (#110810 )

2024-11-06 00:20:21 +03:00

fixed-vectors-vsub-vp-mask.ll

[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404 )

2023-09-06 10:43:41 +01:00

fixed-vectors-vsub-vp.ll

[RISCV][CFI] add function epilogue cfi information (#110810 )

2024-11-06 00:20:21 +03:00

fixed-vectors-vw-web-simplification.ll

[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404 )

2023-09-06 10:43:41 +01:00

fixed-vectors-vwadd-mask.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-vwadd.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-vwaddu.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-vwmacc.ll

[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404 )

2023-09-06 10:43:41 +01:00

fixed-vectors-vwmaccsu.ll

[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404 )

2023-09-06 10:43:41 +01:00

fixed-vectors-vwmaccu.ll

[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404 )

2023-09-06 10:43:41 +01:00

fixed-vectors-vwmaccus.ll

[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404 )

2023-09-06 10:43:41 +01:00

fixed-vectors-vwmul.ll

[RISCV] Implement isHighLatencyDef() (#127476 )

2025-02-18 14:24:20 +08:00

fixed-vectors-vwmulsu.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-vwmulu.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-vwsll.ll

[RISCV] Fold vector shift of sext/zext to widening multiply (#121563 )

2025-02-04 16:59:57 +01:00

fixed-vectors-vwsub-mask.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-vwsub.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-vwsubu.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fixed-vectors-vxor-vp.ll

[RISCV][CFI] add function epilogue cfi information (#110810 )

2024-11-06 00:20:21 +03:00

fixed-vectors-xsfvcp-x.ll

[RISCV][SiFive] Reduce intrinsics of SiFive VCIX extension (#79407 )

2024-01-26 11:15:53 +08:00

fixed-vectors-xsfvcp-xv.ll

[RISCV] Remove blank lines at the end of testcases. NFC.

2024-01-02 13:13:04 +08:00

fixed-vectors-xsfvcp-xvv.ll

[RISCV][VCIX] Add a tied constraint between rd and rs3 in sf.v.xvv and sf.v.xvw instructions (#111630 )

2024-10-14 21:10:55 -07:00

fixed-vectors-xsfvcp-xvw.ll

[RISCV] Remove blank lines at the end of testcases. NFC.

2024-01-02 13:13:04 +08:00

fixed-vectors-zext-vp-mask.ll

[RISCV] Convert more constant splats in tests to splat shorthand. NFC (#87616 )

2024-04-09 15:46:38 +08:00

fixed-vectors-zext-vp.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

float-round-conv.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

floor-vp.ll

[RISCV] Move VMV0 elimination past machine SSA opts (#126850 )

2025-02-20 12:41:05 +08:00

fmaximum-sdnode.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fmaximum-vp.ll

[RISCV] Delete dead COPYs to vmv0 during vmv0 elimination

2025-02-26 23:09:50 +08:00

fminimum-sdnode.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fminimum-vp.ll

[RISCV] Delete dead COPYs to vmv0 during vmv0 elimination

2025-02-26 23:09:50 +08:00

fnearbyint-constrained-sdnode.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fnearbyint-sdnode.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fold-binary-reduce.ll

[RISCV][VLOPT] Add support for checkUsers when UserMI is a Single-Width Integer Reduction (#120345 )

2025-01-07 17:56:07 -05:00

fold-binop-into-select.ll

[DAGCombiner][RISCV] Handle truncating splats in isNeutralConstant (#87338 )

2024-04-04 12:36:15 +08:00

fold-scalar-load-crash.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fold-vector-cmp.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fold-vp-fadd-and-vp-fmul.ll

[RISCV] Convert more constant splats in tests to splat shorthand. NFC (#87616 )

2024-04-09 15:46:38 +08:00

fold-vp-fsub-and-vp-fmul.ll

…

fpclamptosat_vec.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fptosi-sat.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

fptoui-sat.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

frameindex-addr.ll

[CodeGen] Convert tests to opaque pointers (NFC)

2024-02-05 14:07:09 +01:00

frint-sdnode.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445 )

2024-11-15 17:53:14 +08:00

frm-insert.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fround-constrained-sdnode.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fround-sdnode.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

froundeven-constrained-sdnode.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

froundeven-sdnode.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

fshr-fshl-vp.ll

[RISCV] Delete dead COPYs to vmv0 during vmv0 elimination

2025-02-26 23:09:50 +08:00

fshr-fshl.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445 )

2024-11-15 17:53:14 +08:00

ftrunc-constrained-sdnode.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445 )

2024-11-15 17:53:14 +08:00

ftrunc-sdnode.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445 )

2024-11-15 17:53:14 +08:00

get_vector_length.ll

[RISCV] Use PromoteSetCCOperands to promote operands for UMAX/UMIN during type legalization. (#82716 )

2024-02-26 10:31:58 -08:00

get-vlen-debugloc.mir

[RISCV][CFI] add function epilogue cfi information (#110810 )

2024-11-06 00:20:21 +03:00

half-round-conv.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

handle-noreg-with-implicit-def.mir

[CodeGen] Add generic INIT_UNDEF pseudo (#106744 )

2024-09-05 09:34:39 +02:00

implicit-def-copy.ll

[RISCV] Select mask operands as virtual registers and eliminate uses of vmv0 (#125026 )

2025-02-12 12:06:55 +08:00

inline-asm.ll

[RISCV] Clear vill for whole vector register moves in vsetvli insertion (#118283 )

2024-12-06 00:48:05 +08:00

insert-subvector.ll

[RISCV] Clear vill for whole vector register moves in vsetvli insertion (#118283 )

2024-12-06 00:48:05 +08:00

insertelt-fp.ll

[RISCV] Move bfloat tests back above half. NFC

2024-10-02 15:30:49 +08:00

insertelt-i1.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445 )

2024-11-15 17:53:14 +08:00

insertelt-int-rv32.ll

[RISCV] Remove unncessary FP extensions from some integer only vector tests.

2024-07-31 15:21:03 -07:00

insertelt-int-rv64.ll

[RISCV] Remove unncessary FP extensions from some integer only vector tests.

2024-07-31 15:21:03 -07:00

interleave-crash.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445 )

2024-11-15 17:53:14 +08:00

intrinsic-vector-match.ll

[RISCV] Update matchSplatAsGather to use the index of extract_elt if in-bounds (#118873 )

2025-01-21 12:51:41 -08:00

known-never-zero.ll

[RISCV][CFI] add function epilogue cfi information (#110810 )

2024-11-06 00:20:21 +03:00

large-rvv-stack-size.mir

[RISCV][CFI] add function epilogue cfi information (#110810 )

2024-11-06 00:20:21 +03:00

legalize-load-sdnode.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

legalize-scalable-vectortype.ll

…

legalize-store-sdnode.ll

[RISCV] Remove unncessary FP extensions from some integer only vector tests.

2024-07-31 15:21:03 -07:00

llrint-sdnode.ll

CodeGen/RISCV: increase test coverage of lrint, llrint (#70826 )

2023-10-31 19:16:39 +00:00

llrint-vp.ll

[RISCV] Clear vill for whole vector register moves in vsetvli insertion (#118283 )

2024-12-06 00:48:05 +08:00

load-add-store.ll

[RISCV] Prefer vsetivli for VLMAX when VLEN is exactly known (#75509 )

2024-01-17 12:40:00 -08:00

load-bf16.ll

[RISCV] Expand bf16 vector truncstores and extloads (#108235 )

2024-09-12 08:42:25 +08:00

load-mask.ll

[CodeGen] Convert tests to opaque pointers (NFC)

2024-02-05 14:07:09 +01:00

localvar.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

lrint-sdnode.ll

[RISCV] Fix missing CHECK prefixes in vector lrint test files. NFC

2024-04-08 16:01:18 -07:00

lrint-vp.ll

[RISCV] Clear vill for whole vector register moves in vsetvli insertion (#118283 )

2024-12-06 00:48:05 +08:00

marith-vp.ll

[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404 )

2023-09-06 10:43:41 +01:00

mask-exts-not.ll

[RISCV] Avoid VMNOT by swapping VMERGE operands for mask extensions (#126751 )

2025-02-20 13:53:21 +01:00

mask-exts-truncs.ll

[RISCV] Merge more rv32/rv64 intrtinsic tests that have (or should have) the same content. NFC

2024-07-30 16:20:37 -07:00

mask-reg-alloc.mir

[RISCV] Adjust RISCVVectorMaskDAGMutation to look for copy to V0 (#129296 )

2025-03-05 08:56:09 -08:00

masked-load-fp.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

masked-load-int.ll

[RISCV] Convert more constant splats in tests to splat shorthand. NFC (#87616 )

2024-04-09 15:46:38 +08:00

masked-store-fp.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

masked-store-int.ll

[RISCV] Convert more constant splats in tests to splat shorthand. NFC (#87616 )

2024-04-09 15:46:38 +08:00

masked-tama.ll

[RISCV] Use opaque pointers in some tests. NFC (#127906 )

2025-02-19 15:16:09 -08:00

masked-tamu.ll

[RISCV] Use opaque pointers in some tests. NFC (#127906 )

2025-02-19 15:16:09 -08:00

masked-tuma.ll

[RISCV] Use opaque pointers in some tests. NFC (#127906 )

2025-02-19 15:16:09 -08:00

masked-tumu.ll

[RISCV] Use opaque pointers in some tests. NFC (#127906 )

2025-02-19 15:16:09 -08:00

masked-vslide1down-rv32.ll

…

memcpy-crash-zvl32b.ll

[RISCV] Disable fixed vectors in getOptimalMemOpType if minimum VLEN is 32. (#102974 )

2024-08-12 20:55:13 -07:00

memcpy-inline.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

memory-args.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

memset-inline.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445 )

2024-11-15 17:53:14 +08:00

mgather-sdnode.ll

[RISCV] Adjust RISCVVectorMaskDAGMutation to look for copy to V0 (#129296 )

2025-03-05 08:56:09 -08:00

mscatter-combine.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445 )

2024-11-15 17:53:14 +08:00

mscatter-sdnode.ll

[RISCV] Adjust RISCVVectorMaskDAGMutation to look for copy to V0 (#129296 )

2025-03-05 08:56:09 -08:00

mul-combine.ll

[RISCV] Combine vXi32 (mul (and (lshr X, 15), 0x10001), 0xffff) -> (bitcast (sra (v2Xi16 (bitcast X)), 15)) (#93565 )

2024-05-28 15:54:44 -07:00

mutate-prior-vsetvli-avl.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

named-vector-shuffle-reverse.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

narrow-shift-extend.ll

[RISCV][VLOPT] Add vmerge to isSupportedInstr (#122340 )

2025-01-09 16:10:40 -05:00

nearbyint-vp.ll

[RISCV] Delete dead COPYs to vmv0 during vmv0 elimination

2025-02-26 23:09:50 +08:00

no-reserved-frame.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

pass-fast-math-flags-sdnode.ll

[RISCV] Select mask operands as virtual registers and eliminate uses of vmv0 (#125026 )

2025-02-12 12:06:55 +08:00

pr52475.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445 )

2024-11-15 17:53:14 +08:00

pr61561.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445 )

2024-11-15 17:53:14 +08:00

pr63459.ll

[RISCV][VLOPT] Add vector indexed loads and stores to getOperandInfo (#119748 )

2024-12-17 23:51:45 -05:00

pr63596.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

pr64588.ll

…

pr83017.ll

[RISCV] Move exact VLEN VLMAX transform to RISCVVectorPeephole (#100551 )

2024-07-26 07:56:12 +08:00

pr83920.ll

[DAGCombiner] Handle extending EXTRACT_VECTOR_ELTs in calculateByteProvider (#83963 )

2024-03-05 18:31:33 +08:00

pr88576.ll

[RISCV] Clear vill for whole vector register moves in vsetvli insertion (#118283 )

2024-12-06 00:48:05 +08:00

pr88799.ll

[RISCV] Change how MMO is rebuilt in lowerFixedLengthVectorLoadToRVV/lowerFixedLengthVectorStoreToRVV (#88811 )

2024-04-15 22:39:09 -07:00

pr90559.ll

[RISCV] Move exact VLEN VLMAX transform to RISCVVectorPeephole (#100551 )

2024-07-26 07:56:12 +08:00

pr93587.ll

[RISCV][CFI] add function epilogue cfi information (#110810 )

2024-11-06 00:20:21 +03:00

pr95865.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

pr99782.ll

[RISCV] Update test for #99821 after #100116 . NFC

2024-07-24 12:10:45 +08:00

pr104480.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445 )

2024-11-15 17:53:14 +08:00

pr106109.ll

[RISCV] Fix v[f]slide1down.vx having VL changed (#106110 )

2024-08-29 12:50:12 +08:00

pr107950.ll

[RISCV] Mark pointer masking extensions as non-experimental (#113618 )

2024-10-25 12:24:50 +01:00

pr125306.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

reduce-vl-peephole.ll

[RISCV] Check VL dominates and potentially move in tryReduceVL (#106753 )

2024-08-31 01:50:24 +08:00

reduce-vl-peephole.mir

[RISCV] Check VL dominates and potentially move in tryReduceVL (#106753 )

2024-08-31 01:50:24 +08:00

reg-alloc-reserve-bp.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

reg-coalescing.mir

…

regalloc-fast-crash.ll

[llvm][RISCV] Support RISCV vector tuple CodeGen and Calling Convention (#97995 )

2024-08-31 19:28:36 +08:00

remat.ll

[RISCV][CFI] add function epilogue cfi information (#110810 )

2024-11-06 00:20:21 +03:00

rint-vp.ll

[LegalizeVectorOps][RISCV] Use VP_FP_EXTEND/ROUND when promoting VP_FP* operations. (#122784 )

2025-01-13 15:18:41 -08:00

riscv-codegenprepare-asm.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445 )

2024-11-15 17:53:14 +08:00

riscv-codegenprepare.ll

[RISCV] Vectorize phi for loop carried @llvm.vector.reduce.fadd (#78244 )

2024-01-18 16:15:20 +07:00

round-vp.ll

[RISCV] Move VMV0 elimination past machine SSA opts (#126850 )

2025-02-20 12:41:05 +08:00

roundeven-vp.ll

[RISCV] Move VMV0 elimination past machine SSA opts (#126850 )

2025-02-20 12:41:05 +08:00

roundtozero-vp.ll

[RISCV] Move VMV0 elimination past machine SSA opts (#126850 )

2025-02-20 12:41:05 +08:00

rv32-spill-vector-csr.ll

[RISCV] Allow spilling to unused Zcmp Stack (#125959 )

2025-02-06 19:45:47 -08:00

rv32-spill-vector.ll

[RISCV] Take known minimum vlen into account when calculating alignment padding in assignRVVStackObjectOffsets. (#110312 )

2024-09-30 11:44:23 -07:00

rv32-spill-zvlsseg.ll

[RISCV] Clear vill for whole vector register moves in vsetvli insertion (#118283 )

2024-12-06 00:48:05 +08:00

rv32-zve-bitcast-crash.ll

[RISCV] Don't create BuildPairF64 or SplitF64 nodes without D or Zdinx. (#116159 )

2024-11-14 09:54:33 -08:00

rv64-spill-vector-csr.ll

[RISCV] Clear vill for whole vector register moves in vsetvli insertion (#118283 )

2024-12-06 00:48:05 +08:00

rv64-spill-vector.ll

[RISCV] Add explicit VLS test line for vector spill/fill

2024-11-22 11:55:24 -08:00

rv64-spill-zvlsseg.ll

[RISCV] Clear vill for whole vector register moves in vsetvli insertion (#118283 )

2024-12-06 00:48:05 +08:00

rvv-args-by-mem.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

rvv-cfi-info.ll

[RISCV] Fix double counting scalar CSRs with Zcmp when emitting cfi_offset for RVV CSRs. (#117408 )

2024-11-25 10:03:48 -08:00

rvv-framelayout.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445 )

2024-11-15 17:53:14 +08:00

rvv-out-arguments.ll

[RISCV] Add unit strided load/store to whole register peephole (#100116 )

2024-07-24 11:52:54 +08:00

rvv-peephole-vmerge-masked-vops.ll

[RISCV] Reduce VL of vmerge.vvm's true operand (#105786 )

2024-08-27 01:11:46 +08:00

rvv-peephole-vmerge-to-vmv.mir

[RISCV] Select mask operands as virtual registers and eliminate uses of vmv0 (#125026 )

2025-02-12 12:06:55 +08:00

rvv-peephole-vmerge-vops-mir.ll

[RISCV] Select mask operands as virtual registers and eliminate uses of vmv0 (#125026 )

2025-02-12 12:06:55 +08:00

rvv-peephole-vmerge-vops.ll

[RISCV][VLOpt] Put vmclr/vmset back in the RISCVVPseudo table. (#128293 )

2025-02-22 15:30:35 -08:00

rvv-stack-align.mir

[MachineFrameInfo] Refactoring around computeMaxcallFrameSize() (NFC) (#78001 )

2024-03-18 10:37:59 -04:00

rvv-vmerge-to-vmv.ll

[RISCV] Convert more constant splats in tests to splat shorthand. NFC (#87616 )

2024-04-09 15:46:38 +08:00

rvv-vscale.i32.ll

…

rvv-vscale.i64.ll

[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404 )

2023-09-06 10:43:41 +01:00

saddo-sdnode.ll

…

scalable-vector-struct.ll

[CodeGen] Convert tests to opaque pointers (NFC)

2024-02-05 14:07:09 +01:00

scalar-stack-align.ll

[RISCV] Take known minimum vlen into account when calculating alignment padding in assignRVVStackObjectOffsets. (#110312 )

2024-09-30 11:44:23 -07:00

select-bf16.ll

[RISCV] Remove experimental for bf16 extensions (#97996 )

2024-07-09 14:34:03 +08:00

select-fp.ll

[RISCV] Remove duplicate bf16 testing. NFC

2024-06-13 20:05:24 -07:00

select-int.ll

…

select-sra.ll

[RISCV] Strip W suffix from ADDIW (#68425 )

2023-10-06 10:28:01 -07:00

setcc-fp-vp.ll

[RISCV] Delete dead COPYs to vmv0 during vmv0 elimination

2025-02-26 23:09:50 +08:00

setcc-fp.ll

[RISCV] Don't custom lower direct fp_extends where possible (#125644 )

2025-02-05 12:29:26 +08:00

setcc-int-vp-mask.ll

…

setcc-int-vp.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

setcc-integer.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445 )

2024-11-15 17:53:14 +08:00

sf_vfnrclip_x_f_qf.ll

[RISCV] Add hasPostISelHook to sf.vfnrclip pseudo instructions. (#114274 )

2024-10-30 11:52:49 -07:00

sf_vfnrclip_xu_f_qf.ll

[RISCV] Add hasPostISelHook to sf.vfnrclip pseudo instructions. (#114274 )

2024-10-30 11:52:49 -07:00

sf_vfwmacc_4x4x4.ll

[RISCV] Remove experimental for bf16 extensions (#97996 )

2024-07-09 14:34:03 +08:00

sf_vqmacc_2x8x2.ll

[RISCV] Add missing lmul info for SiFive extensions (#76006 )

2023-12-20 14:42:47 +08:00

sf_vqmacc_4x8x4.ll

Recommit [RISCV] Update the interface of sifive vqmaccqoq (#74284 ) (#75768 )

2023-12-26 12:59:00 +08:00

sf_vqmaccsu_2x8x2.ll

[RISCV] Add missing lmul info for SiFive extensions (#76006 )

2023-12-20 14:42:47 +08:00

sf_vqmaccsu_4x8x4.ll

Recommit [RISCV] Update the interface of sifive vqmaccqoq (#74284 ) (#75768 )

2023-12-26 12:59:00 +08:00

sf_vqmaccu_2x8x2.ll

[RISCV] Add missing lmul info for SiFive extensions (#76006 )

2023-12-20 14:42:47 +08:00

sf_vqmaccu_4x8x4.ll

Recommit [RISCV] Update the interface of sifive vqmaccqoq (#74284 ) (#75768 )

2023-12-26 12:59:00 +08:00

sf_vqmaccus_2x8x2.ll

[RISCV] Add missing lmul info for SiFive extensions (#76006 )

2023-12-20 14:42:47 +08:00

sf_vqmaccus_4x8x4.ll

Recommit [RISCV] Update the interface of sifive vqmaccqoq (#74284 ) (#75768 )

2023-12-26 12:59:00 +08:00

shrinkwrap.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

sink-splat-operands-i1.ll

Revert "[LSR][TTI][RISCV] Disable terminator folding for RISC-V."

2024-01-11 13:20:02 -08:00

sink-splat-operands.ll

[RISCV] Implement isHighLatencyDef() (#127476 )

2025-02-18 14:24:20 +08:00

smulo-sdnode.ll

…

splat-vector-split-i64-vl-sdnode.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445 )

2024-11-15 17:53:14 +08:00

splat-vectors.ll

[RISCV] Update matchSplatAsGather to use the index of extract_elt if in-bounds (#118873 )

2025-01-21 12:51:41 -08:00

splats-with-mixed-vl.ll

[DAG] Restrict insert_subvector undef, splat_veector, dontcare transform

2023-08-18 12:44:09 -07:00

sshl_sat_vec.ll

[RISCV] Set a barrier between mask producer and user of V0 (#114012 )

2024-11-29 13:25:53 +08:00

stack-coloring-scalablevec.mir

…

stack-folding.ll

[RISCV][CFI] add function epilogue cfi information (#110810 )

2024-11-06 00:20:21 +03:00

stack-probing-dynamic.ll

[RISCV] Stack clash protection for dynamic alloca (#122508 )

2025-01-16 11:58:42 -08:00

stack-probing-rvv.ll

[RISCV] Add stack clash vector support (#119458 )

2025-01-10 09:48:21 -08:00

stepvector.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

store-bf16.ll

[RISCV] Expand bf16 vector truncstores and extloads (#108235 )

2024-09-12 08:42:25 +08:00

strided-load-store.ll

[RISCV] Allow non-loop invariant steps in RISCVGatherScatterLowering (#122244 )

2025-01-17 08:58:56 +08:00

strided-vpload-vpstore-output.ll

[RISCV] Select mask operands as virtual registers and eliminate uses of vmv0 (#125026 )

2025-02-12 12:06:55 +08:00

strided-vpload.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

strided-vpstore.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

subregister-undef-early-clobber.mir

[InitUndef] Don't use largest super class (#107885 )

2024-09-11 09:36:20 +02:00

tail-agnostic-impdef-copy.mir

[NewPM][CodeGen] Port finalize-isel to new pass manager (#94214 )

2024-06-04 09:23:52 +08:00

trunc-sat-clip-sdnode.ll

[RISCV] Don't support TRUNCATE_SSAT_U. (#104468 )

2024-08-16 08:42:36 -07:00

trunc-select-to-max-usat.ll

[RISCV] Don't support TRUNCATE_SSAT_U. (#104468 )

2024-08-16 08:42:36 -07:00

umulo-sdnode.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

unaligned-loads-stores.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

undef-earlyclobber-chain.ll

[RISCV] Clear vill for whole vector register moves in vsetvli insertion (#118283 )

2024-12-06 00:48:05 +08:00

undef-earlyclobber-chain.mir

[win] NFC: Rename EHCatchret to EHCont to allow for EH Continuation targets that aren't catchret instructions (#129953 )

2025-03-06 09:28:44 -08:00

undef-vp-ops.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

unmasked-ta.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

unmasked-tu.ll

[RISCV] Use opaque pointers in some tests. NFC (#127906 )

2025-02-19 15:16:09 -08:00

urem-seteq-vec.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

ushl_sat_vec.ll

…

vaadd.ll

[RISCV] Enable store clustering by default (#73796 )

2024-10-11 20:25:53 +01:00

vaaddu-sdnode.ll

[RISCV][CFI] add function epilogue cfi information (#110810 )

2024-11-06 00:20:21 +03:00

vaaddu.ll

[RISCV] Enable store clustering by default (#73796 )

2024-10-11 20:25:53 +01:00

vadc.ll

[RISCV] Enable store clustering by default (#73796 )

2024-10-11 20:25:53 +01:00

vadd-sdnode.ll

[RISCV][CFI] add function epilogue cfi information (#110810 )

2024-11-06 00:20:21 +03:00

vadd-vp-mask.ll

…

vadd-vp.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

vadd.ll

[RISCV] Enable store clustering by default (#73796 )

2024-10-11 20:25:53 +01:00

vaesdf.ll

[RISCV] Remove blank lines at the end of testcases. NFC.

2024-01-02 13:13:04 +08:00

vaesdm.ll

[RISCV] Remove blank lines at the end of testcases. NFC.

2024-01-02 13:13:04 +08:00

vaesef.ll

[RISCV] Remove blank lines at the end of testcases. NFC.

2024-01-02 13:13:04 +08:00

vaesem.ll

[RISCV] Remove blank lines at the end of testcases. NFC.

2024-01-02 13:13:04 +08:00

vaeskf1.ll

[RISCV] Remove experimental from Vector Crypto extensions (#74213 )

2023-12-18 22:04:22 -08:00

vaeskf2.ll

[RISCV] Remove experimental from Vector Crypto extensions (#74213 )

2023-12-18 22:04:22 -08:00

vaesz.ll

[RISCV] Remove blank lines at the end of testcases. NFC.

2024-01-02 13:13:04 +08:00

vand-sdnode.ll

[RISCV][CFI] add function epilogue cfi information (#110810 )

2024-11-06 00:20:21 +03:00

vand-vp.ll

[RISCV][VLOPT] Add strided, unit strided, and indexed loads to isSupported (#121705 )

2025-01-07 17:45:06 -05:00

vand.ll

[RISCV] Enable store clustering by default (#73796 )

2024-10-11 20:25:53 +01:00

vandn-sdnode.ll

[RISCV] Select Zvkb VANDN for shorter constant loading sequences (#123345 )

2025-01-22 07:42:27 +01:00

vandn-vp.ll

[RISCV] Select Zvkb VANDN for shorter constant loading sequences (#123345 )

2025-01-22 07:42:27 +01:00

vandn.ll

[RISCV] Enable store clustering by default (#73796 )

2024-10-11 20:25:53 +01:00

variant-cc.ll

…

vasub.ll

[RISCV] Enable store clustering by default (#73796 )

2024-10-11 20:25:53 +01:00

vasubu.ll

[RISCV] Enable store clustering by default (#73796 )

2024-10-11 20:25:53 +01:00

vbrev8.ll

[RISCV] Remove experimental from Vector Crypto extensions (#74213 )

2023-12-18 22:04:22 -08:00

vbrev.ll

[RISCV] Remove experimental from Vector Crypto extensions (#74213 )

2023-12-18 22:04:22 -08:00

vclmul.ll

[RISCV] Enable store clustering by default (#73796 )

2024-10-11 20:25:53 +01:00

vclmulh.ll

[RISCV] Enable store clustering by default (#73796 )

2024-10-11 20:25:53 +01:00

vclz.ll

[RISCV] Remove experimental from Vector Crypto extensions (#74213 )

2023-12-18 22:04:22 -08:00

vcompress.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vcopysign-vp.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vcpop-compute-known-bits.ll

[RISCVISel] Compute leading zeros for RISCVISD::VCPOP_VL node (#127705 )

2025-02-19 11:39:55 +03:00

vcpop-shl-zext-opt.ll

[RISCVISel] Compute leading zeros for RISCVISD::VCPOP_VL node (#127705 )

2025-02-19 11:39:55 +03:00

vcpop.ll

[RISCV] Clear vill for whole vector register moves in vsetvli insertion (#118283 )

2024-12-06 00:48:05 +08:00

vcpopv.ll

[RISCV] Remove experimental from Vector Crypto extensions (#74213 )

2023-12-18 22:04:22 -08:00

vctz.ll

[RISCV] Remove experimental from Vector Crypto extensions (#74213 )

2023-12-18 22:04:22 -08:00

vdiv-sdnode.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445 )

2024-11-15 17:53:14 +08:00

vdiv-vp.ll

[RISCV][VLOPT] Add strided, unit strided, and indexed loads to isSupported (#121705 )

2025-01-07 17:45:06 -05:00

vdiv.ll

[RISCV] Enable store clustering by default (#73796 )

2024-10-11 20:25:53 +01:00

vdivu-sdnode.ll

[RISCV][CFI] add function epilogue cfi information (#110810 )

2024-11-06 00:20:21 +03:00

vdivu-vp.ll

[RISCV][VLOPT] Add strided, unit strided, and indexed loads to isSupported (#121705 )

2025-01-07 17:45:06 -05:00

vdivu.ll

[RISCV] Enable store clustering by default (#73796 )

2024-10-11 20:25:53 +01:00

vec3-setcc-crash.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445 )

2024-11-15 17:53:14 +08:00

vector-compress.ll

[RISCV] Lower @llvm.experimental.vector.compress for zvfhmin/zvfbfmin (#113770 )

2024-10-28 09:37:06 +00:00

vector-deinterleave-fixed.ll

[RISCV] Adjust RISCVVectorMaskDAGMutation to look for copy to V0 (#129296 )

2025-03-05 08:56:09 -08:00

vector-deinterleave-load.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

vector-deinterleave.ll

[RISCV] Adjust RISCVVectorMaskDAGMutation to look for copy to V0 (#129296 )

2025-03-05 08:56:09 -08:00

vector-extract-last-active.ll

[RISCV] Move VMV0 elimination past machine SSA opts (#126850 )

2025-02-20 12:41:05 +08:00

vector-interleave-fixed.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

vector-interleave-store.ll

[IA] Generalize the support for power-of-two (de)interleave intrinsics (#123863 )

2025-01-23 15:27:51 -08:00

vector-interleave.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

vector-reassociations.ll

[RISCV] Move VMV0 elimination past machine SSA opts (#126850 )

2025-02-20 12:41:05 +08:00

vector-splice.ll

[RISCV] Clear vill for whole vector register moves in vsetvli insertion (#118283 )

2024-12-06 00:48:05 +08:00

vector-tuple-align.ll

[RISCV] Tuple intrinsics are creating overly aligned memory operands (#115804 )

2024-11-15 14:12:07 +08:00

vexts-sdnode.ll

[RISCV] Remove blank lines at the end of testcases. NFC.

2024-01-02 13:13:04 +08:00

vfabs-sdnode.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfabs-vp.ll

[RISCV] Clear vill for whole vector register moves in vsetvli insertion (#118283 )

2024-12-06 00:48:05 +08:00

vfadd-constrained-sdnode.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445 )

2024-11-15 17:53:14 +08:00

vfadd-sdnode.ll

[RISCV] Don't custom lower direct fp_extends where possible (#125644 )

2025-02-05 12:29:26 +08:00

vfadd-vp.ll

[RISCV] Delete dead COPYs to vmv0 during vmv0 elimination

2025-02-26 23:09:50 +08:00

vfadd.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfclass-sdnode.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfclass-vp.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfclass.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfcmp-constrained-sdnode.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445 )

2024-11-15 17:53:14 +08:00

vfcmps-constrained-sdnode.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445 )

2024-11-15 17:53:14 +08:00

vfcopysign-sdnode.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445 )

2024-11-15 17:53:14 +08:00

vfcvt-f-x.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfcvt-f-xu.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfcvt-rtz-x-f.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfcvt-rtz-xu-f.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfcvt-x-f.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfcvt-xu-f.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfdiv-constrained-sdnode.ll

[RISCV] Implement isHighLatencyDef() (#127476 )

2025-02-18 14:24:20 +08:00

vfdiv-sdnode.ll

[RISCV] Implement isHighLatencyDef() (#127476 )

2025-02-18 14:24:20 +08:00

vfdiv-vp.ll

[RISCV] Delete dead COPYs to vmv0 during vmv0 elimination

2025-02-26 23:09:50 +08:00

vfdiv.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfirst-byte-compare-index.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445 )

2024-11-15 17:53:14 +08:00

vfirst.ll

[RISCV] Clear vill for whole vector register moves in vsetvli insertion (#118283 )

2024-12-06 00:48:05 +08:00

vfma-vp-combine.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

vfma-vp.ll

[RISCV] Delete dead COPYs to vmv0 during vmv0 elimination

2025-02-26 23:09:50 +08:00

vfmacc-vp.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfmacc.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfmadd-constrained-sdnode.ll

[RISCV] Clear vill for whole vector register moves in vsetvli insertion (#118283 )

2024-12-06 00:48:05 +08:00

vfmadd-sdnode.ll

[RISCV] Don't custom lower direct fp_extends where possible (#125644 )

2025-02-05 12:29:26 +08:00

vfmadd.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfmax-sdnode.ll

[RISCV] Don't custom lower direct fp_extends where possible (#125644 )

2025-02-05 12:29:26 +08:00

vfmax-vp.ll

[RISCV] Delete dead COPYs to vmv0 during vmv0 elimination

2025-02-26 23:09:50 +08:00

vfmax.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfmerge.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfmin-sdnode.ll

[RISCV] Don't custom lower direct fp_extends where possible (#125644 )

2025-02-05 12:29:26 +08:00

vfmin-vp.ll

[RISCV] Delete dead COPYs to vmv0 during vmv0 elimination

2025-02-26 23:09:50 +08:00

vfmin.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfmsac-vp.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfmsac.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfmsub-constrained-sdnode.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445 )

2024-11-15 17:53:14 +08:00

vfmsub-sdnode.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfmsub.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfmul-constrained-sdnode.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445 )

2024-11-15 17:53:14 +08:00

vfmul-sdnode.ll

[RISCV] Don't custom lower direct fp_extends where possible (#125644 )

2025-02-05 12:29:26 +08:00

vfmul-vp.ll

[RISCV] Delete dead COPYs to vmv0 during vmv0 elimination

2025-02-26 23:09:50 +08:00

vfmul.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfmuladd-vp.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

vfmv.f.s.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfmv.s.f.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfmv.v.f.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfncvt-f-f.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfncvt-f-x.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfncvt-f-xu.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfncvt-rod-f-f.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfncvt-rtz-x-f.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfncvt-rtz-xu-f.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfncvt-x-f.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfncvt-xu-f.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfncvtbf16-f-f.ll

[RISCV] Remove experimental for bf16 extensions (#97996 )

2024-07-09 14:34:03 +08:00

vfneg-sdnode.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfneg-vp.ll

[RISCV] Clear vill for whole vector register moves in vsetvli insertion (#118283 )

2024-12-06 00:48:05 +08:00

vfnmacc-vp.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfnmacc.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfnmadd-constrained-sdnode.ll

[RISCV] Clear vill for whole vector register moves in vsetvli insertion (#118283 )

2024-12-06 00:48:05 +08:00

vfnmadd-sdnode.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfnmadd.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfnmsac-vp.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfnmsac.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfnmsub-constrained-sdnode.ll

[RISCV] Clear vill for whole vector register moves in vsetvli insertion (#118283 )

2024-12-06 00:48:05 +08:00

vfnmsub-sdnode.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfnmsub.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfpext-constrained-sdnode.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfpext-sdnode.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfpext-vp.ll

[RISCV] Clear vill for whole vector register moves in vsetvli insertion (#118283 )

2024-12-06 00:48:05 +08:00

vfptoi-constrained-sdnode.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfptoi-sdnode.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445 )

2024-11-15 17:53:14 +08:00

vfptosi-vp-mask.ll

[RISCV][VLOPT] Add floating point widening and narrowing bf16 convert support (#122353 )

2025-01-13 15:38:03 -05:00

vfptosi-vp.ll

[RISCV] Delete dead COPYs to vmv0 during vmv0 elimination

2025-02-26 23:09:50 +08:00

vfptoui-vp-mask.ll

[RISCV][VLOPT] Add floating point widening and narrowing bf16 convert support (#122353 )

2025-01-13 15:38:03 -05:00

vfptoui-vp.ll

[RISCV] Delete dead COPYs to vmv0 during vmv0 elimination

2025-02-26 23:09:50 +08:00

vfptrunc-constrained-sdnode.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfptrunc-sdnode.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfptrunc-vp.ll

[RISCV] Delete dead COPYs to vmv0 during vmv0 elimination

2025-02-26 23:09:50 +08:00

vfrdiv-vp.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfrdiv.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfrec7.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfredmax.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfredmin.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfredosum.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfredusum.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfrsqrt7.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfrsub-vp.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfrsub.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfsgnj.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfsgnjn.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfsgnjx.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfslide1down.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfslide1up.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfsqrt-constrained-sdnode.ll

[RISCV] Implement isHighLatencyDef() (#127476 )

2025-02-18 14:24:20 +08:00

vfsqrt-sdnode.ll

[RISCV] Implement isHighLatencyDef() (#127476 )

2025-02-18 14:24:20 +08:00

vfsqrt-vp.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

vfsqrt.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfsub-constrained-sdnode.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445 )

2024-11-15 17:53:14 +08:00

vfsub-sdnode.ll

[RISCV] Don't custom lower direct fp_extends where possible (#125644 )

2025-02-05 12:29:26 +08:00

vfsub-vp.ll

[RISCV] Delete dead COPYs to vmv0 during vmv0 elimination

2025-02-26 23:09:50 +08:00

vfsub.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfwadd-sdnode.ll

[RISCV] Match widening fp instructions with same fpext used in multiple operands (#125803 )

2025-02-11 01:11:44 +08:00

vfwadd-vp.ll

[RISCV] Restrict combineOp_VLToVWOp_VL w/ bf16 to vfwmadd_vl with zvfbfwma (#108798 )

2024-09-17 13:35:25 +08:00

vfwadd.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfwadd.w.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfwcvt-f-f.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfwcvt-f-x.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfwcvt-f-xu.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfwcvt-rtz-x-f.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfwcvt-rtz-xu-f.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfwcvt-x-f.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfwcvt-xu-f.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfwcvtbf16-f-f.ll

[RISCV] Remove experimental for bf16 extensions (#97996 )

2024-07-09 14:34:03 +08:00

vfwmacc-sdnode.ll

[RISCV] Match widening fp instructions with same fpext used in multiple operands (#125803 )

2025-02-11 01:11:44 +08:00

vfwmacc-vp.ll

[RISCV][VLOPT] Add Vector FP instructions to getOperandInfo (#121609 )

2025-01-05 11:19:08 -05:00

vfwmacc.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfwmaccbf16-sdnode.ll

[RISCV] Add scalable vector patterns for vfwmaccbf16.v{v,f} (#106771 )

2024-08-31 13:20:19 +08:00

vfwmaccbf16.ll

[RISCV] Remove experimental for bf16 extensions (#97996 )

2024-07-09 14:34:03 +08:00

vfwmsac-vp.ll

[RISCV][VLOPT] Add Vector FP instructions to getOperandInfo (#121609 )

2025-01-05 11:19:08 -05:00

vfwmsac.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfwmul-sdnode.ll

[RISCV] Match widening fp instructions with same fpext used in multiple operands (#125803 )

2025-02-11 01:11:44 +08:00

vfwmul.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfwnmacc-vp.ll

[RISCV][VLOPT] Add Vector FP instructions to getOperandInfo (#121609 )

2025-01-05 11:19:08 -05:00

vfwnmacc.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfwnmsac-vp.ll

[RISCV][VLOPT] Add Vector FP instructions to getOperandInfo (#121609 )

2025-01-05 11:19:08 -05:00

vfwnmsac.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfwredosum.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfwredusum.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfwsub-sdnode.ll

[RISCV] Match widening fp instructions with same fpext used in multiple operands (#125803 )

2025-02-11 01:11:44 +08:00

vfwsub.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vfwsub.w.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vghsh.ll

[RISCV] Remove experimental from Vector Crypto extensions (#74213 )

2023-12-18 22:04:22 -08:00

vgmul.ll

[RISCV] Remove experimental from Vector Crypto extensions (#74213 )

2023-12-18 22:04:22 -08:00

vid.ll

…

viota.ll

…

vitofp-constrained-sdnode.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vitofp-sdnode.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445 )

2024-11-15 17:53:14 +08:00

vl-opt-evl-tail-folding.ll

[VPlan] Don't convert widen recipes to VP intrinsics in EVL transform (#127180 )

2025-02-22 19:38:11 +08:00

vl-opt-instrs.ll

[RISCV][VLOPT] Add vfsqrt/vfrsqrt7 instruction to isSupportInstr (#127462 )

2025-02-19 14:11:16 +08:00

vl-opt-no-prop.ll

[RISCV][VLOPT] Update test cases to use riscv-enable-vl-optimizer and better formatting

2024-10-14 08:44:16 -07:00

vl-opt-op-info.ll

[RISCV][VLOPT] Enable the RISCVVLOptimizer by default (#119461 )

2024-12-17 16:19:35 -05:00

vl-opt-op-info.mir

[RISCV][VLOpt] Put vmclr/vmset back in the RISCVVPseudo table. (#128293 )

2025-02-22 15:30:35 -08:00

vl-opt-user-scalar-def.mir

[RISCV][VLOPT] Avoid crash when user produces scalar def (#120255 )

2024-12-17 12:07:29 -05:00

vl-opt.ll

[RISCV][VLOPT] Peek through copies in checkUsers (#127656 )

2025-02-20 12:01:06 +08:00

vl-opt.mir

[RISCV][VLOPT] Peek through copies in checkUsers (#127656 )

2025-02-20 12:01:06 +08:00

vle_vid-vfcvt.ll

[RISCV] Always use signed APSInt in getExactInteger. (#84070 )

2024-03-05 14:36:37 -08:00

vle.ll

[RISCV] Replace Zvfh with Zvfhmin on vector load/store intrinsic tests. NFC

2024-07-31 23:30:44 -07:00

vleff-vlseg2ff-output.ll

[RISCV] Select mask operands as virtual registers and eliminate uses of vmv0 (#125026 )

2025-02-12 12:06:55 +08:00

vleff.ll

[RISCV] Use opaque pointers in some tests. NFC (#127906 )

2025-02-19 15:16:09 -08:00

vlm.ll

[CodeGen] Convert tests to opaque pointers (NFC)

2024-02-05 14:07:09 +01:00

vlmax-peephole.ll

[RISCV] Convert AVLs with vlenb to VLMAX where possible (#97800 )

2024-07-11 14:22:00 +08:00

vlopt-same-vl.ll

[RISCV][VLOPT] Compute demanded VLs up front (#124530 )

2025-01-29 12:39:38 +08:00

vlopt-volatile-ld.mir

[RISCV][VLOPT] Add strided, unit strided, and indexed loads to isSupported (#121705 )

2025-01-07 17:45:06 -05:00

vloxei-rv64.ll

[RISCV] Replace Zvfh with Zvfhmin on vector load/store intrinsic tests. NFC

2024-07-31 23:30:44 -07:00

vloxei.ll

[RISCV] Replace Zvfh with Zvfhmin on vector load/store intrinsic tests. NFC

2024-07-31 23:30:44 -07:00

vloxseg-rv32.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vloxseg-rv64.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vlse.ll

[RISCV] Replace Zvfh with Zvfhmin on vector load/store intrinsic tests. NFC

2024-07-31 23:30:44 -07:00

vlseg-rv32.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vlseg-rv64.ll

[RISCV] Mark RVV stores and segmented loads as masked pseudo (#123106 )

2025-01-21 09:37:22 -08:00

vlsegff-rv32-dead.ll

[RISCV] Clear vill for whole vector register moves in vsetvli insertion (#118283 )

2024-12-06 00:48:05 +08:00

vlsegff-rv32.ll

[RISCV] Clear vill for whole vector register moves in vsetvli insertion (#118283 )

2024-12-06 00:48:05 +08:00

vlsegff-rv64-dead.ll

[RISCV] Clear vill for whole vector register moves in vsetvli insertion (#118283 )

2024-12-06 00:48:05 +08:00

vlsegff-rv64.ll

[RISCV] Clear vill for whole vector register moves in vsetvli insertion (#118283 )

2024-12-06 00:48:05 +08:00

vlsseg-rv32.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vlsseg-rv64.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vluxei-rv64.ll

[RISCV] Replace Zvfh with Zvfhmin on vector load/store intrinsic tests. NFC

2024-07-31 23:30:44 -07:00

vluxei.ll

[RISCV] Replace Zvfh with Zvfhmin on vector load/store intrinsic tests. NFC

2024-07-31 23:30:44 -07:00

vluxseg-rv32.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vluxseg-rv64.ll

[RISCV] Mark RVV stores and segmented loads as masked pseudo (#123106 )

2025-01-21 09:37:22 -08:00

vmacc-vp.ll

[RISCV][VLOPT] Add strided, unit strided, and indexed loads to isSupported (#121705 )

2025-01-07 17:45:06 -05:00

vmacc.ll

[RISCV] Enable store clustering by default (#73796 )

2024-10-11 20:25:53 +01:00

vmadc.carry.in.ll

[RISCV] Enable store clustering by default (#73796 )

2024-10-11 20:25:53 +01:00

vmadc.ll

[RISCV] Enable store clustering by default (#73796 )

2024-10-11 20:25:53 +01:00

vmadd-sdnode.ll

[RISCV][CFI] add function epilogue cfi information (#110810 )

2024-11-06 00:20:21 +03:00

vmadd-vp.ll

[RISCV][VLOPT] Allow users that are passthrus if tail elements aren't demanded (#124066 )

2025-01-30 23:45:24 +08:00

vmadd.ll

[RISCV] Enable store clustering by default (#73796 )

2024-10-11 20:25:53 +01:00

vmand.ll

…

vmandn.ll

…

vmarith-sdnode.ll

[RISCV] Convert more constant splats in tests to splat shorthand. NFC (#87616 )

2024-04-09 15:46:38 +08:00

vmax-sdnode.ll

[RISCV][CFI] add function epilogue cfi information (#110810 )

2024-11-06 00:20:21 +03:00

vmax-vp.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

vmax.ll

[RISCV] Enable store clustering by default (#73796 )

2024-10-11 20:25:53 +01:00

vmaxu-sdnode.ll

[RISCV][CFI] add function epilogue cfi information (#110810 )

2024-11-06 00:20:21 +03:00

vmaxu-vp.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

vmaxu.ll

[RISCV] Enable store clustering by default (#73796 )

2024-10-11 20:25:53 +01:00

vmclr.ll

…

vmerge.ll

[RISCV] Add IR tests for bf16 vmerge and vmv.v.v. NFC (#102775 )

2024-08-10 22:39:46 -07:00

vmfeq.ll

[RISCV] Clear vill for whole vector register moves in vsetvli insertion (#118283 )

2024-12-06 00:48:05 +08:00

vmfge.ll

[RISCV] Clear vill for whole vector register moves in vsetvli insertion (#118283 )

2024-12-06 00:48:05 +08:00

vmfgt.ll

[RISCV] Clear vill for whole vector register moves in vsetvli insertion (#118283 )

2024-12-06 00:48:05 +08:00

vmfle.ll

[RISCV] Clear vill for whole vector register moves in vsetvli insertion (#118283 )

2024-12-06 00:48:05 +08:00

vmflt.ll

[RISCV] Clear vill for whole vector register moves in vsetvli insertion (#118283 )

2024-12-06 00:48:05 +08:00

vmfne.ll

[RISCV] Clear vill for whole vector register moves in vsetvli insertion (#118283 )

2024-12-06 00:48:05 +08:00

vmin-sdnode.ll

[RISCV][CFI] add function epilogue cfi information (#110810 )

2024-11-06 00:20:21 +03:00

vmin-vp.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

vmin.ll

[RISCV] Enable store clustering by default (#73796 )

2024-10-11 20:25:53 +01:00

vminu-sdnode.ll

[RISCV][CFI] add function epilogue cfi information (#110810 )

2024-11-06 00:20:21 +03:00

vminu-vp.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

vminu.ll

[RISCV] Enable store clustering by default (#73796 )

2024-10-11 20:25:53 +01:00

vmnand.ll

…

vmnor.ll

…

vmor.ll

…

vmorn.ll

…

vmsbc.borrow.in.ll

[RISCV] Enable store clustering by default (#73796 )

2024-10-11 20:25:53 +01:00

vmsbc.ll

[RISCV] Enable store clustering by default (#73796 )

2024-10-11 20:25:53 +01:00

vmsbf.ll

[RISCV] Clear vill for whole vector register moves in vsetvli insertion (#118283 )

2024-12-06 00:48:05 +08:00

vmseq.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

vmset.ll

…

vmsge.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

vmsgeu.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

vmsgt.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

vmsgtu.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

vmsif.ll

[RISCV] Clear vill for whole vector register moves in vsetvli insertion (#118283 )

2024-12-06 00:48:05 +08:00

vmsle.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

vmsleu.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

vmslt.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

vmsltu.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

vmsne.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

vmsof.ll

[RISCV] Clear vill for whole vector register moves in vsetvli insertion (#118283 )

2024-12-06 00:48:05 +08:00

vmul-sdnode.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445 )

2024-11-15 17:53:14 +08:00

vmul-vp-mask.ll

…

vmul-vp.ll

[RISCV][VLOPT] Add strided, unit strided, and indexed loads to isSupported (#121705 )

2025-01-07 17:45:06 -05:00

vmul.ll

[RISCV] Enable store clustering by default (#73796 )

2024-10-11 20:25:53 +01:00

vmulh-sdnode.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445 )

2024-11-15 17:53:14 +08:00

vmulh.ll

[RISCV] Enable store clustering by default (#73796 )

2024-10-11 20:25:53 +01:00

vmulhsu.ll

[RISCV] Enable store clustering by default (#73796 )

2024-10-11 20:25:53 +01:00

vmulhu-sdnode.ll

[RISCV] Convert more constant splats in tests to splat shorthand. NFC (#87616 )

2024-04-09 15:46:38 +08:00

vmulhu.ll

[RISCV] Enable store clustering by default (#73796 )

2024-10-11 20:25:53 +01:00

vmv0-elimination.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

vmv0-elimination.mir

[RISCV] Delete dead COPYs to vmv0 during vmv0 elimination

2025-02-26 23:09:50 +08:00

vmv-copy.mir

[CodeGen][NPM] Port ExpandPostRAPseudos to NPM (#129509 )

2025-03-04 11:49:09 +05:30

vmv.s.x.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

vmv.v.v-peephole.ll

[RISCV] Clear vill for whole vector register moves in vsetvli insertion (#118283 )

2024-12-06 00:48:05 +08:00

vmv.v.v-peephole.mir

[RISCV] Model dest EEW and fix peepholes not checking EEW (#105945 )

2024-09-05 15:27:48 +08:00

vmv.v.v.ll

[RISCV] Add passthru to vmv.v.v intrinsic tests. NFC

2024-09-04 13:51:32 +08:00

vmv.v.x.ll

[RISCV] Enable store clustering by default (#73796 )

2024-10-11 20:25:53 +01:00

vmv.x.s.ll

[RISCV] Merge more rv32/rv64 intrtinsic tests that have (or should have) the same content. NFC

2024-07-30 16:20:37 -07:00

vmxnor.ll

…

vmxor.ll

…

vnclip.ll

[RISCV] Move RISCVInsertVSETVLI after CSR/VXRM passes (#91701 )

2024-05-10 14:31:43 +08:00

vnclipu.ll

[RISCV] Move RISCVInsertVSETVLI after CSR/VXRM passes (#91701 )

2024-05-10 14:31:43 +08:00

vnmsac-vp.ll

[RISCV][VLOPT] Add strided, unit strided, and indexed loads to isSupported (#121705 )

2025-01-07 17:45:06 -05:00

vnmsac.ll

[RISCV] Enable store clustering by default (#73796 )

2024-10-11 20:25:53 +01:00

vnmsub-sdnode.ll

[RISCV][CFI] add function epilogue cfi information (#110810 )

2024-11-06 00:20:21 +03:00

vnmsub.ll

[RISCV] Enable store clustering by default (#73796 )

2024-10-11 20:25:53 +01:00

vnsra-sdnode.ll

[RISCV] Convert more constant splats in tests to splat shorthand. NFC (#87616 )

2024-04-09 15:46:38 +08:00

vnsra-vp.ll

[RISCV] Convert more constant splats in tests to splat shorthand. NFC (#87616 )

2024-04-09 15:46:38 +08:00

vnsra.ll

…

vnsrl-sdnode.ll

[RISCV] Convert more constant splats in tests to splat shorthand. NFC (#87616 )

2024-04-09 15:46:38 +08:00

vnsrl-vp.ll

[RISCV] Convert more constant splats in tests to splat shorthand. NFC (#87616 )

2024-04-09 15:46:38 +08:00

vnsrl.ll

…

vor-sdnode.ll

[RISCV][CFI] add function epilogue cfi information (#110810 )

2024-11-06 00:20:21 +03:00

vor-vp.ll

[RISCV][VLOPT] Add strided, unit strided, and indexed loads to isSupported (#121705 )

2025-01-07 17:45:06 -05:00

vor.ll

[RISCV] Enable store clustering by default (#73796 )

2024-10-11 20:25:53 +01:00

vp-combine-reverse-load.ll

[RISCV] Use getSignedConstant for negative values. (#125903 )

2025-02-05 14:49:01 -08:00

vp-combine-store-reverse.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

vp-cttz-elts.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

vp-inttoptr-ptrtoint.ll

[RISCV] Add missing tests for inttoptr/ptrtoint on scalable vectors (#77857 )

2024-01-12 09:52:07 -08:00

vp-reverse-float-fixed-vectors.ll

[RISCV] Convert more constant splats in tests to splat shorthand. NFC (#87616 )

2024-04-09 15:46:38 +08:00

vp-reverse-float.ll

[RISCV] Convert more constant splats in tests to splat shorthand. NFC (#87616 )

2024-04-09 15:46:38 +08:00

vp-reverse-int-fixed-vectors.ll

[RISCV] Convert more constant splats in tests to splat shorthand. NFC (#87616 )

2024-04-09 15:46:38 +08:00

vp-reverse-int.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445 )

2024-11-15 17:53:14 +08:00

vp-reverse-mask-fixed-vectors.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445 )

2024-11-15 17:53:14 +08:00

vp-reverse-mask.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445 )

2024-11-15 17:53:14 +08:00

vp-select.ll

[RISCV] Clear vill for whole vector register moves in vsetvli insertion (#118283 )

2024-12-06 00:48:05 +08:00

vp-splat.ll

[RISCV][CFI] add function epilogue cfi information (#110810 )

2024-11-06 00:20:21 +03:00

vp-splice-fixed-vectors.ll

[RISCV] Convert more constant splats in tests to splat shorthand. NFC (#87616 )

2024-04-09 15:46:38 +08:00

vp-splice-mask-fixed-vectors.ll

[RISCV] Clear vill for whole vector register moves in vsetvli insertion (#118283 )

2024-12-06 00:48:05 +08:00

vp-splice-mask-vectors.ll

[RISCV] Clear vill for whole vector register moves in vsetvli insertion (#118283 )

2024-12-06 00:48:05 +08:00

vp-splice.ll

[RISCV] Convert more constant splats in tests to splat shorthand. NFC (#87616 )

2024-04-09 15:46:38 +08:00

vp-vaaddu.ll

[RISCV] Add DAG combine for forming VAADDU_VL from VP intrinsics. (#124848 )

2025-01-30 09:03:00 -08:00

vp-vector-interleaved-access.ll

[RISCV] Move VMV0 elimination past machine SSA opts (#126850 )

2025-02-20 12:41:05 +08:00

vpgather-sdnode.ll

[RISCV] Move VMV0 elimination past machine SSA opts (#126850 )

2025-02-20 12:41:05 +08:00

vpload.ll

[RISCV] Move VMV0 elimination past machine SSA opts (#126850 )

2025-02-20 12:41:05 +08:00

vpmerge-sdnode-bf16.ll

[RISCV] Lower f16/bf16 splat_vector by bitcasting to i16 instead of promoting to f32. (#108298 )

2024-09-11 22:29:20 -07:00

vpmerge-sdnode.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

vpscatter-sdnode.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

vpstore.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

vredand.ll

[RISCV] Use TU policy for C reduction intrinsics. (#93970 )

2024-05-31 14:03:02 -05:00

vredmax.ll

[RISCV] Use TU policy for C reduction intrinsics. (#93970 )

2024-05-31 14:03:02 -05:00

vredmaxu.ll

[RISCV] Use TU policy for C reduction intrinsics. (#93970 )

2024-05-31 14:03:02 -05:00

vredmin.ll

[RISCV] Use TU policy for C reduction intrinsics. (#93970 )

2024-05-31 14:03:02 -05:00

vredminu.ll

[RISCV] Use TU policy for C reduction intrinsics. (#93970 )

2024-05-31 14:03:02 -05:00

vredor.ll

[RISCV] Use TU policy for C reduction intrinsics. (#93970 )

2024-05-31 14:03:02 -05:00

vredsum.ll

[RISCV] Use TU policy for C reduction intrinsics. (#93970 )

2024-05-31 14:03:02 -05:00

vreductions-fp-sdnode-bf16.ll

[SelectionDAG][RISCV] Promote VECREDUCE_{FMAX,FMIN,FMAXIMUM,FMINIMUM} (#128800 )

2025-02-28 23:13:30 +08:00

vreductions-fp-sdnode-f16.ll

[SelectionDAG][RISCV] Promote VECREDUCE_{FMAX,FMIN,FMAXIMUM,FMINIMUM} (#128800 )

2025-02-28 23:13:30 +08:00

vreductions-fp-sdnode.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

vreductions-fp-vp-bf16.ll

[SelectionDAG][RISCV] Promote VECREDUCE_{FMAX,FMIN,FMAXIMUM,FMINIMUM} (#128800 )

2025-02-28 23:13:30 +08:00

vreductions-fp-vp-f16.ll

[SelectionDAG][RISCV] Promote VECREDUCE_{FMAX,FMIN,FMAXIMUM,FMINIMUM} (#128800 )

2025-02-28 23:13:30 +08:00

vreductions-fp-vp.ll

[RISCV] The test for vp.reduce.fminimum/fmaximum with fixed-length should stay in fixed-vectors-reduction-fp-vp.ll. (NFC)

2025-02-26 10:32:57 +08:00

vreductions-int-vp.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445 )

2024-11-15 17:53:14 +08:00

vreductions-int.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445 )

2024-11-15 17:53:14 +08:00

vreductions-mask-vp.ll

[RISCV] Clear vill for whole vector register moves in vsetvli insertion (#118283 )

2024-12-06 00:48:05 +08:00

vreductions-mask.ll

[RISCV] Use ISD::XOR instead of RISCVISD::VMXOR_VL in lowerVectorMaskVecReduction of scalable ISD::VECREDUCE_AND (#121812 )

2025-01-06 14:26:21 -08:00

vredxor.ll

[RISCV] Use TU policy for C reduction intrinsics. (#93970 )

2024-05-31 14:03:02 -05:00

vrem-sdnode.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445 )

2024-11-15 17:53:14 +08:00

vrem-vp.ll

[RISCV][VLOPT] Add strided, unit strided, and indexed loads to isSupported (#121705 )

2025-01-07 17:45:06 -05:00

vrem.ll

[RISCV] Enable store clustering by default (#73796 )

2024-10-11 20:25:53 +01:00

vremu-sdnode.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445 )

2024-11-15 17:53:14 +08:00

vremu-vp.ll

[RISCV][VLOPT] Add strided, unit strided, and indexed loads to isSupported (#121705 )

2025-01-07 17:45:06 -05:00

vremu.ll

[RISCV] Enable store clustering by default (#73796 )

2024-10-11 20:25:53 +01:00

vrev8.ll

[RISCV] Remove experimental from Vector Crypto extensions (#74213 )

2023-12-18 22:04:22 -08:00

vrgather.ll

[RISCV] Support vrgather and vcompress for zvfhmin and zvfbfmin (#101633 )

2024-08-06 18:00:16 +08:00

vrgatherei16-subreg-liveness.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

vrgatherei16.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vrol-sdnode.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445 )

2024-11-15 17:53:14 +08:00

vrol.ll

[RISCV] Remove experimental from Vector Crypto extensions (#74213 )

2023-12-18 22:04:22 -08:00

vror-sdnode.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445 )

2024-11-15 17:53:14 +08:00

vror.ll

[RISCV] Remove experimental from Vector Crypto extensions (#74213 )

2023-12-18 22:04:22 -08:00

vrsub-sdnode.ll

[RISCV][CFI] add function epilogue cfi information (#110810 )

2024-11-06 00:20:21 +03:00

vrsub-vp.ll

[RISCV][VLOPT] Add strided, unit strided, and indexed loads to isSupported (#121705 )

2025-01-07 17:45:06 -05:00

vrsub.ll

[RISCV] Enable store clustering by default (#73796 )

2024-10-11 20:25:53 +01:00

vsadd-sdnode.ll

[RISCV][CFI] add function epilogue cfi information (#110810 )

2024-11-06 00:20:21 +03:00

vsadd-vp.ll

[RISCV][VLOPT] Add strided, unit strided, and indexed loads to isSupported (#121705 )

2025-01-07 17:45:06 -05:00

vsadd.ll

[RISCV] Enable store clustering by default (#73796 )

2024-10-11 20:25:53 +01:00

vsaddu-sdnode.ll

[RISCV][CFI] add function epilogue cfi information (#110810 )

2024-11-06 00:20:21 +03:00

vsaddu-vp.ll

[RISCV][VLOPT] Add strided, unit strided, and indexed loads to isSupported (#121705 )

2025-01-07 17:45:06 -05:00

vsaddu.ll

[RISCV] Enable store clustering by default (#73796 )

2024-10-11 20:25:53 +01:00

vsbc.ll

[RISCV] Enable store clustering by default (#73796 )

2024-10-11 20:25:53 +01:00

vscale-power-of-two.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445 )

2024-11-15 17:53:14 +08:00

vscale-vw-web-simplification.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

vse.ll

[RISCV] Mark RVV stores and segmented loads as masked pseudo (#123106 )

2025-01-21 09:37:22 -08:00

vselect-bf16.ll

[RISCV] Clear vill for whole vector register moves in vsetvli insertion (#118283 )

2024-12-06 00:48:05 +08:00

vselect-fp.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

vselect-int.ll

[RISCV] Clear vill for whole vector register moves in vsetvli insertion (#118283 )

2024-12-06 00:48:05 +08:00

vselect-mask.ll

…

vselect-vp-bf16.ll

[RISCV] Remove Zfbfmin from some vector test RUN lines. NFC

2024-07-31 22:25:23 -07:00

vselect-vp.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

vsetvl-ext.ll

[RISCV][DAG] Teach computeKnownBits consider SEW/LMUL/AVL for vsetvli. (#76158 )

2023-12-25 11:18:22 +08:00

vsetvli-insert-crossbb.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

vsetvli-insert-crossbb.mir

[RISCV] Use _B* suffix for vector mask logic pseudo instructions. (#119787 )

2024-12-12 21:11:01 -08:00

vsetvli-insert-O0.ll

[RISCV] Clear vill for whole vector register moves in vsetvli insertion (#118283 )

2024-12-06 00:48:05 +08:00

vsetvli-insert-zve64f.mir

[RISCV] Swap the order of SEWGreaterThanOrEqualAndLessThan64 and SEWGreaterThanOrEqual. (#120649 )

2024-12-20 11:26:19 -08:00

vsetvli-insert.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

vsetvli-insert.mir

[RISCV] Add missing implicit $vtype to vector copies in mir tests. NFC

2025-01-31 16:24:32 +08:00

vsetvli-intrinsics.ll

[CodeGen] Convert tests to opaque pointers (NFC)

2024-02-05 14:07:09 +01:00

vsetvli-regression.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

vsetvli-valid-elen-fp.ll

[RISCV] Keep same SEW/LMUL ratio if possible in forward transfer (#69788 )

2023-10-27 12:16:28 +01:00

vsetvlmax-ext.ll

[RISCV][DAG] Teach computeKnownBits consider SEW/LMUL/AVL for vsetvli. (#76158 )

2023-12-25 11:18:22 +08:00

vsext-vp-mask.ll

[LLVM][tests/CodeGen/RISCV] Convert instances of ConstantExpr based splats to use splat().

2024-02-27 13:37:23 +00:00

vsext-vp.ll

[RISCV] Clear vill for whole vector register moves in vsetvli insertion (#118283 )

2024-12-06 00:48:05 +08:00

vsext.ll

…

vsha2ch.ll

[RISCV] Remove experimental from Vector Crypto extensions (#74213 )

2023-12-18 22:04:22 -08:00

vsha2cl.ll

[RISCV] Remove experimental from Vector Crypto extensions (#74213 )

2023-12-18 22:04:22 -08:00

vsha2ms.ll

[RISCV] Remove experimental from Vector Crypto extensions (#74213 )

2023-12-18 22:04:22 -08:00

vshl-sdnode.ll

[RISCV] Convert more constant splats in tests to splat shorthand. NFC (#87616 )

2024-04-09 15:46:38 +08:00

vshl-vp.ll

[RISCV][VLOPT] Enable the RISCVVLOptimizer by default (#119461 )

2024-12-17 16:19:35 -05:00

vsitofp-vp-mask.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vsitofp-vp.ll

[RISCV] Delete dead COPYs to vmv0 during vmv0 elimination

2025-02-26 23:09:50 +08:00

vslide1down-constant-vl-rv32.ll

[RISCV] Use X0 for VLMax for slide1up/slide1down in lowerVectorIntrinsicScalars. (#101384 )

2024-07-31 13:01:31 -07:00

vslide1down.ll

[RISCV] Merge more rv32/rv64 intrtinsic tests that have (or should have) the same content. NFC

2024-07-30 16:20:37 -07:00

vslide1up-constant-vl-rv32.ll

[RISCV] Use X0 for VLMax for slide1up/slide1down in lowerVectorIntrinsicScalars. (#101384 )

2024-07-31 13:01:31 -07:00

vslide1up.ll

[RISCV] Merge more rv32/rv64 intrtinsic tests that have (or should have) the same content. NFC

2024-07-30 16:20:37 -07:00

vslidedown.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vslideup.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vsll.ll

[RISCV] Make the vsll->vadd intrinsic pattern support tail undisturbed intrinsics.

2024-06-05 11:34:41 -07:00

vsm3c.ll

[RISCV] Remove experimental from Vector Crypto extensions (#74213 )

2023-12-18 22:04:22 -08:00

vsm3me.ll

[RISCV] Remove experimental from Vector Crypto extensions (#74213 )

2023-12-18 22:04:22 -08:00

vsm4k.ll

[RISCV] Remove experimental from Vector Crypto extensions (#74213 )

2023-12-18 22:04:22 -08:00

vsm4r.ll

[RISCV] Remove blank lines at the end of testcases. NFC.

2024-01-02 13:13:04 +08:00

vsm.ll

[CodeGen] Convert tests to opaque pointers (NFC)

2024-02-05 14:07:09 +01:00

vsmul.ll

[RISCV] Enable store clustering by default (#73796 )

2024-10-11 20:25:53 +01:00

vsoxei-rv64.ll

[RISCV] Replace Zvfh with Zvfhmin on vector load/store intrinsic tests. NFC

2024-07-31 23:30:44 -07:00

vsoxei.ll

[RISCV] Replace Zvfh with Zvfhmin on vector load/store intrinsic tests. NFC

2024-07-31 23:30:44 -07:00

vsoxseg-rv32.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vsoxseg-rv64.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vsplats-bf16.ll

[RISCV] Lower f16/bf16 splat_vector by bitcasting to i16 instead of promoting to f32. (#108298 )

2024-09-11 22:29:20 -07:00

vsplats-f16.ll

[RISCV] Lower f16/bf16 splat_vector by bitcasting to i16 instead of promoting to f32. (#108298 )

2024-09-11 22:29:20 -07:00

vsplats-fp.ll

[RISCV] Add splat tests for zvfbfmin and without zfhmin/zfbfmin. NFC

2024-09-25 19:41:17 +08:00

vsplats-i1.ll

[RISCV] Convert more constant splats in tests to splat shorthand. NFC (#87616 )

2024-04-09 15:46:38 +08:00

vsplats-i64.ll

[RISCV][CFI] add function epilogue cfi information (#110810 )

2024-11-06 00:20:21 +03:00

vsplats-zfa.ll

[RISCV] Convert more constant splats in tests to splat shorthand. NFC (#87616 )

2024-04-09 15:46:38 +08:00

vsra-sdnode.ll

[RISCV][VLOPT] Enable the RISCVVLOptimizer by default (#119461 )

2024-12-17 16:19:35 -05:00

vsra-vp.ll

[RISCV][VLOPT] Enable the RISCVVLOptimizer by default (#119461 )

2024-12-17 16:19:35 -05:00

vsra.ll

…

vsrl-sdnode.ll

[RISCV] Convert more constant splats in tests to splat shorthand. NFC (#87616 )

2024-04-09 15:46:38 +08:00

vsrl-vp.ll

[RISCV][VLOPT] Enable the RISCVVLOptimizer by default (#119461 )

2024-12-17 16:19:35 -05:00

vsrl.ll

…

vsse.ll

[RISCV] Mark RVV stores and segmented loads as masked pseudo (#123106 )

2025-01-21 09:37:22 -08:00

vsseg-rv32.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vsseg-rv64.ll

[RISCV] Mark RVV stores and segmented loads as masked pseudo (#123106 )

2025-01-21 09:37:22 -08:00

vssra-rv32.ll

[RISCV] Move RISCVInsertVSETVLI after CSR/VXRM passes (#91701 )

2024-05-10 14:31:43 +08:00

vssra-rv64.ll

[RISCV] Move RISCVInsertVSETVLI after CSR/VXRM passes (#91701 )

2024-05-10 14:31:43 +08:00

vssrl-rv32.ll

[RISCV] Move RISCVInsertVSETVLI after CSR/VXRM passes (#91701 )

2024-05-10 14:31:43 +08:00

vssrl-rv64.ll

[RISCV] Move RISCVInsertVSETVLI after CSR/VXRM passes (#91701 )

2024-05-10 14:31:43 +08:00

vssseg-rv32.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vssseg-rv64.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vssub-sdnode.ll

[RISCV][CFI] add function epilogue cfi information (#110810 )

2024-11-06 00:20:21 +03:00

vssub-vp.ll

[RISCV][VLOPT] Add strided, unit strided, and indexed loads to isSupported (#121705 )

2025-01-07 17:45:06 -05:00

vssub.ll

[RISCV] Enable store clustering by default (#73796 )

2024-10-11 20:25:53 +01:00

vssubu-sdnode.ll

[RISCV][CFI] add function epilogue cfi information (#110810 )

2024-11-06 00:20:21 +03:00

vssubu-vp.ll

[RISCV][VLOPT] Add strided, unit strided, and indexed loads to isSupported (#121705 )

2025-01-07 17:45:06 -05:00

vssubu.ll

[RISCV] Enable store clustering by default (#73796 )

2024-10-11 20:25:53 +01:00

vsub-sdnode.ll

[RISCV][CFI] add function epilogue cfi information (#110810 )

2024-11-06 00:20:21 +03:00

vsub-vp-mask.ll

…

vsub-vp.ll

[RISCV][VLOPT] Add strided, unit strided, and indexed loads to isSupported (#121705 )

2025-01-07 17:45:06 -05:00

vsub.ll

[RISCV] Enable store clustering by default (#73796 )

2024-10-11 20:25:53 +01:00

vsuxei-rv64.ll

[RISCV] Mark RVV stores and segmented loads as masked pseudo (#123106 )

2025-01-21 09:37:22 -08:00

vsuxei.ll

[RISCV] Replace Zvfh with Zvfhmin on vector load/store intrinsic tests. NFC

2024-07-31 23:30:44 -07:00

vsuxseg-rv32.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vsuxseg-rv64.ll

[RISCV] Mark RVV stores and segmented loads as masked pseudo (#123106 )

2025-01-21 09:37:22 -08:00

vtrunc-vp-mask.ll

[LLVM][tests/CodeGen/RISCV] Convert instances of ConstantExpr based splats to use splat().

2024-02-27 13:37:23 +00:00

vtrunc-vp.ll

[RISCV] Move VMV0 elimination past machine SSA opts (#126850 )

2025-02-20 12:41:05 +08:00

vtruncs-sdnode.ll

[RISCV] Remove blank lines at the end of testcases. NFC.

2024-01-02 13:13:04 +08:00

vuitofp-vp-mask.ll

[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC

2024-10-31 06:51:39 +08:00

vuitofp-vp.ll

[RISCV] Delete dead COPYs to vmv0 during vmv0 elimination

2025-02-26 23:09:50 +08:00

vwadd-mask-sdnode.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

vwadd-sdnode.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

vwadd-vp.ll

[RISCV] Don't require mask or VL to be the same in combineBinOp_VLToVWBinOp_VL (#87997 )

2024-04-09 16:04:10 +08:00

vwadd.ll

…

vwadd.w.ll

…

vwaddu.ll

…

vwaddu.w.ll

…

vwmacc-sdnode.ll

…

vwmacc-vp.ll

[RISCV] Convert more constant splats in tests to splat shorthand. NFC (#87616 )

2024-04-09 15:46:38 +08:00

vwmacc.ll

…

vwmaccsu-vp.ll

[RISCV] Convert more constant splats in tests to splat shorthand. NFC (#87616 )

2024-04-09 15:46:38 +08:00

vwmaccsu.ll

…

vwmaccu-vp.ll

[RISCV] Convert more constant splats in tests to splat shorthand. NFC (#87616 )

2024-04-09 15:46:38 +08:00

vwmaccu.ll

…

vwmaccus.ll

…

vwmul-sdnode.ll

[RISCV] Combine (mul (zext, zext)) -> (zext (mul (zext, zext))) (#86465 )

2024-03-26 23:28:04 +08:00

vwmul.ll

…

vwmulsu.ll

…

vwmulu.ll

…

vwredsum.ll

[RISCV] Use TU policy for C reduction intrinsics. (#93970 )

2024-05-31 14:03:02 -05:00

vwredsumu.ll

[RISCV] Use TU policy for C reduction intrinsics. (#93970 )

2024-05-31 14:03:02 -05:00

vwsll-sdnode.ll

[RISCV] Fold vector shift of sext/zext to widening multiply (#121563 )

2025-02-04 16:59:57 +01:00

vwsll-vp.ll

[RISCV] Fold vector shift of sext/zext to widening multiply (#121563 )

2025-02-04 16:59:57 +01:00

vwsll.ll

[RISCV] Remove experimental from Vector Crypto extensions (#74213 )

2023-12-18 22:04:22 -08:00

vwsub-mask-sdnode.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

vwsub-sdnode.ll

[RISCV] Handle scalable ops with < EEW / 2 narrow types in combineBinOp_VLToVWBinOp_VL (#84158 )

2024-03-22 07:26:29 +08:00

vwsub.ll

…

vwsub.w.ll

…

vwsubu.ll

…

vwsubu.w.ll

…

vxor-sdnode.ll

[RISCV][CFI] add function epilogue cfi information (#110810 )

2024-11-06 00:20:21 +03:00

vxor-vp.ll

[RISCV][VLOPT] Add strided, unit strided, and indexed loads to isSupported (#121705 )

2025-01-07 17:45:06 -05:00

vxor.ll

[RISCV] Enable store clustering by default (#73796 )

2024-10-11 20:25:53 +01:00

vxrm-insert-out-of-loop.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

vxrm-insert.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

vxrm.mir

[RISCV] Move RISCVInsertVSETVLI after CSR/VXRM passes (#91701 )

2024-05-10 14:31:43 +08:00

vzext-vp-mask.ll

[LLVM][tests/CodeGen/RISCV] Convert instances of ConstantExpr based splats to use splat().

2024-02-27 13:37:23 +00:00

vzext-vp.ll

[RISCV] Clear vill for whole vector register moves in vsetvli insertion (#118283 )

2024-12-06 00:48:05 +08:00

vzext.ll

…

wrong-chain-fixed-load.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608 )" and follow up commit.

2025-02-13 09:57:33 -08:00

wrong-stack-offset-for-rvv-object.mir

[RISCV] Take known minimum vlen into account when calculating alignment padding in assignRVVStackObjectOffsets. (#110312 )

2024-09-30 11:44:23 -07:00

wrong-stack-slot-rv32.mir

…

wrong-stack-slot-rv64.mir

…

xsfvcp-x.ll

[RISCV][SiFive] Reduce intrinsics of SiFive VCIX extension (#79407 )

2024-01-26 11:15:53 +08:00

xsfvcp-xv.ll

[RISCV] Remove blank lines at the end of testcases. NFC.

2024-01-02 13:13:04 +08:00

xsfvcp-xvv.ll

[RISCV][VCIX] Add a tied constraint between rd and rs3 in sf.v.xvv and sf.v.xvw instructions (#111630 )

2024-10-14 21:10:55 -07:00

xsfvcp-xvw.ll

[RISCV] Remove blank lines at the end of testcases. NFC.

2024-01-02 13:13:04 +08:00

xtheadvdot-vmaqa.ll

…

xtheadvdot-vmaqasu.ll

…

xtheadvdot-vmaqau.ll

…

xtheadvdot-vmaqaus.ll

…

zvbb-demanded-bits.ll

[RISCV] Handle zvbb instructions in getVectorLowDemandedScalarBits. (#129011 )

2025-03-03 11:27:34 +08:00

zve32-types.ll

[RISCV] Introduce local peephole to reduce VLs based on demanded VL (#104689 )

2024-08-22 07:34:41 -07:00

zvlsseg-copy.mir

[RISCV] Use larger copies when register tuples are aligned

2024-04-08 13:24:57 +08:00

zvlsseg-spill.mir

[RISCV][CFI] add function epilogue cfi information (#110810 )

2024-11-06 00:20:21 +03:00

zvlsseg-zero-vl.ll

[llvm][RISCV] Support RISCV vector tuple CodeGen and Calling Convention (#97995 )

2024-08-31 19:28:36 +08:00