8424bf207e
This patch adds support for the next-generation arch15 CPU architecture to the SystemZ backend. This includes: - Basic support for the new processor and its features. - Detection of arch15 as host processor. - Assembler/disassembler support for new instructions. - Exploitation of new instructions for code generation. - New vector (signed|unsigned|bool) __int128 data types. - New LLVM intrinsics for certain new instructions. - Support for low-level builtins mapped to new LLVM intrinsics. - New high-level intrinsics in vecintrin.h. - Indicate support by defining __VEC__ == 10305. Note: No currently available Z system supports the arch15 architecture. Once new systems become available, the official system name will be added as supported -march name.
59 lines
1.8 KiB
LLVM
59 lines
1.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
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; Test high-part i128->i256 multiplications on arch15.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=arch15 | FileCheck %s
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; Multiply high signed.
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define i128 @f1(i128 %a, i128 %b) {
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; CHECK-LABEL: f1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vl %v0, 0(%r4), 3
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; CHECK-NEXT: vl %v1, 0(%r3), 3
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; CHECK-NEXT: vmhq %v0, %v1, %v0
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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%exta = sext i128 %a to i256
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%extb = sext i128 %b to i256
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%extres = mul i256 %exta, %extb
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%shiftres = lshr i256 %extres, 128
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%res = trunc i256 %shiftres to i128
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ret i128 %res
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}
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; Multiply high unsigned.
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define i128 @f2(i128 %a, i128 %b) {
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; CHECK-LABEL: f2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vl %v0, 0(%r4), 3
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; CHECK-NEXT: vl %v1, 0(%r3), 3
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; CHECK-NEXT: vmlhq %v0, %v1, %v0
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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%exta = zext i128 %a to i256
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%extb = zext i128 %b to i256
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%extres = mul i256 %exta, %extb
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%shiftres = lshr i256 %extres, 128
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%res = trunc i256 %shiftres to i128
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ret i128 %res
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}
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;; ; Multiply-and-add high signed.
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;; define i128 @f3(i128 %a, i128 %b, i128 %add) {
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;; ; CHECX-LABEL: f3:
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;; ; CHECX: # %bb.0:
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;; ; CHECX-NEXT: vl %v0, 0(%r3), 3
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;; ; CHECX-NEXT: vl %v1, 0(%r4), 3
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;; ; CHECX-NEXT: vl %v2, 0(%r5), 3
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;; ; CHECX-NEXT: vmhq %v0, %v0, %v1, %v2
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;; ; CHECX-NEXT: vst %v0, 0(%r2), 3
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;; ; CHECX-NEXT: br %r14
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;; %exta = sext i128 %a to i256
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;; %extb = sext i128 %b to i256
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;; %extadd = sext i128 %add to i256
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;; %extmul = mul i256 %exta, %extb
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;; %extres = add i256 %extmul, %extadd
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;; %shiftres = lshr i256 %extres, 128
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;; %res = trunc i256 %shiftres to i128
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;; ret i128 %res
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;; }
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