58a88001f3
This fixes the handling of subregister extract copies. This will allow AMDGPU to remove its implementation of shouldRewriteCopySrc, which exists as a 10 year old workaround to this bug. peephole-opt-fold-reg-sequence-subreg.mir will show the expected improvement once the custom implementation is removed. The copy coalescing processing here is overly abstracted from what's actually happening. Previously when visiting coalescable copy-like instructions, we would parse the sources one at a time and then pass the def of the root instruction into findNextSource. This means that the first thing the new ValueTracker constructed would do is getVRegDef to find the instruction we are currently processing. This adds an unnecessary step, placing a useless entry in the RewriteMap, and required skipping the no-op case where getNewSource would return the original source operand. This was a problem since in the case of a subregister extract, shouldRewriteCopySource would always say that it is useful to rewrite and the use-def chain walk would abort, returning the original operand. Move the process to start looking at the source operand to begin with. This does not fix the confused handling in the uncoalescable copy case which is proving to be more difficult. Some currently handled cases have multiple defs from a single source, and other handled cases have 0 input operands. It would be simpler if this was implemented with isCopyLikeInstr, rather than guessing at the operand structure as it does now. There are some improvements and some regressions. The regressions appear to be downstream issues for the most part. One of the uglier regressions is in PPC, where a sequence of insert_subrgs is used to build registers. I opened #125502 to use reg_sequence instead, which may help. The worst regression is an absurd SPARC testcase using a <251 x fp128>, which uses a very long chain of insert_subregs. We need improved subregister handling locally in PeepholeOptimizer, and other pasess like MachineCSE to fix some of the other regressions. We should handle subregister composes and folding more indexes into insert_subreg and reg_sequence.
386 lines
12 KiB
LLVM
386 lines
12 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
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; Test 32-bit addition in which the second operand is variable.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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declare i32 @foo()
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; Check ALR.
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define zeroext i1 @f1(i32 %dummy, i32 %a, i32 %b, ptr %res) {
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; CHECK-LABEL: f1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: alr %r3, %r4
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; CHECK-NEXT: ipm %r0
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; CHECK-NEXT: risbg %r2, %r0, 63, 191, 35
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; CHECK-NEXT: st %r3, 0(%r5)
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; CHECK-NEXT: br %r14
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%t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %a, i32 %b)
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%val = extractvalue {i32, i1} %t, 0
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%obit = extractvalue {i32, i1} %t, 1
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store i32 %val, ptr %res
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ret i1 %obit
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}
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; Check using the overflow result for a branch.
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define void @f2(i32 %dummy, i32 %a, i32 %b, ptr %res) {
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; CHECK-LABEL: f2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: alr %r3, %r4
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; CHECK-NEXT: st %r3, 0(%r5)
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; CHECK-NEXT: jgnle foo@PLT
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; CHECK-NEXT: .LBB1_1: # %exit
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; CHECK-NEXT: br %r14
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%t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %a, i32 %b)
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%val = extractvalue {i32, i1} %t, 0
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%obit = extractvalue {i32, i1} %t, 1
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store i32 %val, ptr %res
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br i1 %obit, label %call, label %exit
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call:
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tail call i32 @foo()
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br label %exit
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exit:
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ret void
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}
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; ... and the same with the inverted direction.
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define void @f3(i32 %dummy, i32 %a, i32 %b, ptr %res) {
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; CHECK-LABEL: f3:
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; CHECK: # %bb.0:
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; CHECK-NEXT: alr %r3, %r4
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; CHECK-NEXT: st %r3, 0(%r5)
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; CHECK-NEXT: jgle foo@PLT
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; CHECK-NEXT: .LBB2_1: # %exit
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; CHECK-NEXT: br %r14
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%t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %a, i32 %b)
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%val = extractvalue {i32, i1} %t, 0
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%obit = extractvalue {i32, i1} %t, 1
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store i32 %val, ptr %res
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br i1 %obit, label %exit, label %call
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call:
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tail call i32 @foo()
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br label %exit
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exit:
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ret void
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}
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; Check the low end of the AL range.
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define zeroext i1 @f4(i32 %dummy, i32 %a, ptr %src, ptr %res) {
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; CHECK-LABEL: f4:
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; CHECK: # %bb.0:
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; CHECK-NEXT: al %r3, 0(%r4)
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; CHECK-NEXT: ipm %r0
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; CHECK-NEXT: risbg %r2, %r0, 63, 191, 35
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; CHECK-NEXT: st %r3, 0(%r5)
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; CHECK-NEXT: br %r14
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%b = load i32, ptr %src
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%t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %a, i32 %b)
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%val = extractvalue {i32, i1} %t, 0
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%obit = extractvalue {i32, i1} %t, 1
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store i32 %val, ptr %res
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ret i1 %obit
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}
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; Check the high end of the aligned AL range.
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define zeroext i1 @f5(i32 %dummy, i32 %a, ptr %src, ptr %res) {
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; CHECK-LABEL: f5:
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; CHECK: # %bb.0:
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; CHECK-NEXT: al %r3, 4092(%r4)
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; CHECK-NEXT: ipm %r0
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; CHECK-NEXT: risbg %r2, %r0, 63, 191, 35
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; CHECK-NEXT: st %r3, 0(%r5)
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; CHECK-NEXT: br %r14
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%ptr = getelementptr i32, ptr %src, i64 1023
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%b = load i32, ptr %ptr
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%t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %a, i32 %b)
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%val = extractvalue {i32, i1} %t, 0
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%obit = extractvalue {i32, i1} %t, 1
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store i32 %val, ptr %res
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ret i1 %obit
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}
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; Check the next word up, which should use ALY instead of AL.
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define zeroext i1 @f6(i32 %dummy, i32 %a, ptr %src, ptr %res) {
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; CHECK-LABEL: f6:
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; CHECK: # %bb.0:
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; CHECK-NEXT: aly %r3, 4096(%r4)
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; CHECK-NEXT: ipm %r0
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; CHECK-NEXT: risbg %r2, %r0, 63, 191, 35
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; CHECK-NEXT: st %r3, 0(%r5)
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; CHECK-NEXT: br %r14
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%ptr = getelementptr i32, ptr %src, i64 1024
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%b = load i32, ptr %ptr
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%t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %a, i32 %b)
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%val = extractvalue {i32, i1} %t, 0
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%obit = extractvalue {i32, i1} %t, 1
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store i32 %val, ptr %res
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ret i1 %obit
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}
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; Check the high end of the aligned ALY range.
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define zeroext i1 @f7(i32 %dummy, i32 %a, ptr %src, ptr %res) {
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; CHECK-LABEL: f7:
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; CHECK: # %bb.0:
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; CHECK-NEXT: aly %r3, 524284(%r4)
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; CHECK-NEXT: ipm %r0
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; CHECK-NEXT: risbg %r2, %r0, 63, 191, 35
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; CHECK-NEXT: st %r3, 0(%r5)
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; CHECK-NEXT: br %r14
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%ptr = getelementptr i32, ptr %src, i64 131071
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%b = load i32, ptr %ptr
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%t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %a, i32 %b)
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%val = extractvalue {i32, i1} %t, 0
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%obit = extractvalue {i32, i1} %t, 1
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store i32 %val, ptr %res
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ret i1 %obit
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}
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; Check the next word up, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define zeroext i1 @f8(i32 %dummy, i32 %a, ptr %src, ptr %res) {
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; CHECK-LABEL: f8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: agfi %r4, 524288
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; CHECK-NEXT: al %r3, 0(%r4)
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; CHECK-NEXT: ipm %r0
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; CHECK-NEXT: risbg %r2, %r0, 63, 191, 35
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; CHECK-NEXT: st %r3, 0(%r5)
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; CHECK-NEXT: br %r14
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%ptr = getelementptr i32, ptr %src, i64 131072
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%b = load i32, ptr %ptr
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%t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %a, i32 %b)
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%val = extractvalue {i32, i1} %t, 0
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%obit = extractvalue {i32, i1} %t, 1
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store i32 %val, ptr %res
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ret i1 %obit
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}
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; Check the high end of the negative aligned ALY range.
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define zeroext i1 @f9(i32 %dummy, i32 %a, ptr %src, ptr %res) {
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; CHECK-LABEL: f9:
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; CHECK: # %bb.0:
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; CHECK-NEXT: aly %r3, -4(%r4)
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; CHECK-NEXT: ipm %r0
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; CHECK-NEXT: risbg %r2, %r0, 63, 191, 35
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; CHECK-NEXT: st %r3, 0(%r5)
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; CHECK-NEXT: br %r14
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%ptr = getelementptr i32, ptr %src, i64 -1
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%b = load i32, ptr %ptr
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%t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %a, i32 %b)
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%val = extractvalue {i32, i1} %t, 0
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%obit = extractvalue {i32, i1} %t, 1
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store i32 %val, ptr %res
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ret i1 %obit
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}
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; Check the low end of the ALY range.
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define zeroext i1 @f10(i32 %dummy, i32 %a, ptr %src, ptr %res) {
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; CHECK-LABEL: f10:
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; CHECK: # %bb.0:
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; CHECK-NEXT: aly %r3, -524288(%r4)
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; CHECK-NEXT: ipm %r0
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; CHECK-NEXT: risbg %r2, %r0, 63, 191, 35
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; CHECK-NEXT: st %r3, 0(%r5)
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; CHECK-NEXT: br %r14
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%ptr = getelementptr i32, ptr %src, i64 -131072
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%b = load i32, ptr %ptr
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%t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %a, i32 %b)
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%val = extractvalue {i32, i1} %t, 0
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%obit = extractvalue {i32, i1} %t, 1
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store i32 %val, ptr %res
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ret i1 %obit
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}
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; Check the next word down, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define zeroext i1 @f11(i32 %dummy, i32 %a, ptr %src, ptr %res) {
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; CHECK-LABEL: f11:
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; CHECK: # %bb.0:
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; CHECK-NEXT: agfi %r4, -524292
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; CHECK-NEXT: al %r3, 0(%r4)
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; CHECK-NEXT: ipm %r0
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; CHECK-NEXT: risbg %r2, %r0, 63, 191, 35
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; CHECK-NEXT: st %r3, 0(%r5)
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; CHECK-NEXT: br %r14
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%ptr = getelementptr i32, ptr %src, i64 -131073
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%b = load i32, ptr %ptr
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%t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %a, i32 %b)
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%val = extractvalue {i32, i1} %t, 0
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%obit = extractvalue {i32, i1} %t, 1
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store i32 %val, ptr %res
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ret i1 %obit
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}
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; Check that AL allows an index.
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define zeroext i1 @f12(i64 %src, i64 %index, i32 %a, ptr %res) {
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; CHECK-LABEL: f12:
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; CHECK: # %bb.0:
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; CHECK-NEXT: al %r4, 4092(%r3,%r2)
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; CHECK-NEXT: ipm %r0
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; CHECK-NEXT: risbg %r2, %r0, 63, 191, 35
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; CHECK-NEXT: st %r4, 0(%r5)
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; CHECK-NEXT: br %r14
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%add1 = add i64 %src, %index
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%add2 = add i64 %add1, 4092
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%ptr = inttoptr i64 %add2 to ptr
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%b = load i32, ptr %ptr
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%t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %a, i32 %b)
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%val = extractvalue {i32, i1} %t, 0
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%obit = extractvalue {i32, i1} %t, 1
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store i32 %val, ptr %res
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ret i1 %obit
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}
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; Check that ALY allows an index.
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define zeroext i1 @f13(i64 %src, i64 %index, i32 %a, ptr %res) {
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; CHECK-LABEL: f13:
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; CHECK: # %bb.0:
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; CHECK-NEXT: aly %r4, 4096(%r3,%r2)
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; CHECK-NEXT: ipm %r0
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; CHECK-NEXT: risbg %r2, %r0, 63, 191, 35
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; CHECK-NEXT: st %r4, 0(%r5)
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; CHECK-NEXT: br %r14
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%add1 = add i64 %src, %index
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%add2 = add i64 %add1, 4096
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%ptr = inttoptr i64 %add2 to ptr
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%b = load i32, ptr %ptr
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%t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %a, i32 %b)
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%val = extractvalue {i32, i1} %t, 0
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%obit = extractvalue {i32, i1} %t, 1
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store i32 %val, ptr %res
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ret i1 %obit
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}
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; Check that additions of spilled values can use AL rather than ALR.
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define zeroext i1 @f14(ptr %ptr0) {
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; CHECK-LABEL: f14:
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; CHECK: # %bb.0:
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; CHECK-NEXT: stmg %r6, %r15, 48(%r15)
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; CHECK-NEXT: .cfi_offset %r6, -112
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; CHECK-NEXT: .cfi_offset %r7, -104
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; CHECK-NEXT: .cfi_offset %r8, -96
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; CHECK-NEXT: .cfi_offset %r9, -88
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; CHECK-NEXT: .cfi_offset %r10, -80
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; CHECK-NEXT: .cfi_offset %r11, -72
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; CHECK-NEXT: .cfi_offset %r12, -64
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; CHECK-NEXT: .cfi_offset %r13, -56
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; CHECK-NEXT: .cfi_offset %r14, -48
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; CHECK-NEXT: .cfi_offset %r15, -40
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; CHECK-NEXT: aghi %r15, -168
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; CHECK-NEXT: .cfi_def_cfa_offset 328
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; CHECK-NEXT: l %r7, 0(%r2)
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; CHECK-NEXT: l %r6, 8(%r2)
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; CHECK-NEXT: l %r13, 16(%r2)
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; CHECK-NEXT: l %r12, 24(%r2)
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; CHECK-NEXT: l %r8, 32(%r2)
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; CHECK-NEXT: l %r9, 40(%r2)
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; CHECK-NEXT: l %r10, 48(%r2)
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; CHECK-NEXT: l %r11, 56(%r2)
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; CHECK-NEXT: mvc 160(4,%r15), 64(%r2) # 4-byte Folded Spill
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; CHECK-NEXT: mvc 164(4,%r15), 72(%r2) # 4-byte Folded Spill
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; CHECK-NEXT: brasl %r14, foo@PLT
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; CHECK-NEXT: alr %r2, %r7
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; CHECK-NEXT: ipm %r0
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; CHECK-NEXT: risbg %r0, %r0, 63, 191, 35
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; CHECK-NEXT: alr %r2, %r6
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; CHECK-NEXT: ipm %r1
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; CHECK-NEXT: rosbg %r0, %r1, 63, 63, 35
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; CHECK-NEXT: alr %r2, %r13
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; CHECK-NEXT: ipm %r1
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; CHECK-NEXT: rosbg %r0, %r1, 63, 63, 35
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; CHECK-NEXT: alr %r2, %r12
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; CHECK-NEXT: ipm %r1
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; CHECK-NEXT: rosbg %r0, %r1, 63, 63, 35
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; CHECK-NEXT: alr %r2, %r8
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; CHECK-NEXT: ipm %r1
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; CHECK-NEXT: rosbg %r0, %r1, 63, 63, 35
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; CHECK-NEXT: alr %r2, %r9
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; CHECK-NEXT: ipm %r1
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; CHECK-NEXT: rosbg %r0, %r1, 63, 63, 35
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; CHECK-NEXT: alr %r2, %r10
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; CHECK-NEXT: ipm %r1
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; CHECK-NEXT: rosbg %r0, %r1, 63, 63, 35
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; CHECK-NEXT: alr %r2, %r11
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; CHECK-NEXT: ipm %r1
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; CHECK-NEXT: rosbg %r0, %r1, 63, 63, 35
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; CHECK-NEXT: al %r2, 160(%r15) # 4-byte Folded Reload
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; CHECK-NEXT: ipm %r1
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; CHECK-NEXT: rosbg %r0, %r1, 63, 63, 35
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; CHECK-NEXT: al %r2, 164(%r15) # 4-byte Folded Reload
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; CHECK-NEXT: ipm %r1
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; CHECK-NEXT: rosbg %r0, %r1, 63, 63, 35
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; CHECK-NEXT: risbg %r2, %r0, 63, 191, 0
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; CHECK-NEXT: lmg %r6, %r15, 216(%r15)
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; CHECK-NEXT: br %r14
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%ptr1 = getelementptr i32, ptr %ptr0, i64 2
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%ptr2 = getelementptr i32, ptr %ptr0, i64 4
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%ptr3 = getelementptr i32, ptr %ptr0, i64 6
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%ptr4 = getelementptr i32, ptr %ptr0, i64 8
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%ptr5 = getelementptr i32, ptr %ptr0, i64 10
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%ptr6 = getelementptr i32, ptr %ptr0, i64 12
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%ptr7 = getelementptr i32, ptr %ptr0, i64 14
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%ptr8 = getelementptr i32, ptr %ptr0, i64 16
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%ptr9 = getelementptr i32, ptr %ptr0, i64 18
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%val0 = load i32, ptr %ptr0
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%val1 = load i32, ptr %ptr1
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%val2 = load i32, ptr %ptr2
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%val3 = load i32, ptr %ptr3
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%val4 = load i32, ptr %ptr4
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%val5 = load i32, ptr %ptr5
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%val6 = load i32, ptr %ptr6
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%val7 = load i32, ptr %ptr7
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%val8 = load i32, ptr %ptr8
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%val9 = load i32, ptr %ptr9
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%ret = call i32 @foo()
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%t0 = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %ret, i32 %val0)
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%add0 = extractvalue {i32, i1} %t0, 0
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%obit0 = extractvalue {i32, i1} %t0, 1
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%t1 = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %add0, i32 %val1)
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%add1 = extractvalue {i32, i1} %t1, 0
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%obit1 = extractvalue {i32, i1} %t1, 1
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%res1 = or i1 %obit0, %obit1
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%t2 = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %add1, i32 %val2)
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%add2 = extractvalue {i32, i1} %t2, 0
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%obit2 = extractvalue {i32, i1} %t2, 1
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%res2 = or i1 %res1, %obit2
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%t3 = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %add2, i32 %val3)
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%add3 = extractvalue {i32, i1} %t3, 0
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%obit3 = extractvalue {i32, i1} %t3, 1
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%res3 = or i1 %res2, %obit3
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%t4 = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %add3, i32 %val4)
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%add4 = extractvalue {i32, i1} %t4, 0
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%obit4 = extractvalue {i32, i1} %t4, 1
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%res4 = or i1 %res3, %obit4
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%t5 = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %add4, i32 %val5)
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%add5 = extractvalue {i32, i1} %t5, 0
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%obit5 = extractvalue {i32, i1} %t5, 1
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%res5 = or i1 %res4, %obit5
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%t6 = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %add5, i32 %val6)
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%add6 = extractvalue {i32, i1} %t6, 0
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%obit6 = extractvalue {i32, i1} %t6, 1
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%res6 = or i1 %res5, %obit6
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%t7 = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %add6, i32 %val7)
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%add7 = extractvalue {i32, i1} %t7, 0
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%obit7 = extractvalue {i32, i1} %t7, 1
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%res7 = or i1 %res6, %obit7
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%t8 = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %add7, i32 %val8)
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%add8 = extractvalue {i32, i1} %t8, 0
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%obit8 = extractvalue {i32, i1} %t8, 1
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%res8 = or i1 %res7, %obit8
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%t9 = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %add8, i32 %val9)
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%add9 = extractvalue {i32, i1} %t9, 0
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%obit9 = extractvalue {i32, i1} %t9, 1
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%res9 = or i1 %res8, %obit9
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|
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ret i1 %res9
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}
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declare {i32, i1} @llvm.uadd.with.overflow.i32(i32, i32) nounwind readnone
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