8c0e9adc5c
Add mangling style as a spec entry to datalayout, and implemented importing and exporting LLVM IR to MLIR (LLVM dialect). Its represented as string as the scope of this PR is to preserve info from LLVM IR, so client in MLIR still need to map deduce the meaning of the string, like "e" means ELF, "o" for Mach-O, etc. it addresses one of issues mentioned in this [issue](https://github.com/llvm/llvm-project/issues/126046)
52 lines
1.8 KiB
LLVM
52 lines
1.8 KiB
LLVM
; RUN: mlir-translate -import-llvm -split-input-file %s | FileCheck %s
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; Test the default data layout import.
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; CHECK: dlti.dl_spec =
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; CHECK: #dlti.dl_spec<
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; CHECK-DAG: "dlti.endianness" = "little"
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; CHECK-DAG: i1 = dense<8> : vector<2xi64>
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; CHECK-DAG: i8 = dense<8> : vector<2xi64>
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; CHECK-DAG: i16 = dense<16> : vector<2xi64>
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; CHECK-DAG: i32 = dense<32> : vector<2xi64>
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; CHECK-DAG: i64 = dense<[32, 64]> : vector<2xi64>
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; CHECK-DAG: !llvm.ptr = dense<64> : vector<4xi64>
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; CHECK-DAG: f16 = dense<16> : vector<2xi64>
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; CHECK-DAG: f64 = dense<64> : vector<2xi64>
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; CHECK-DAG: f128 = dense<128> : vector<2xi64>
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; CHECK: >
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target datalayout = ""
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; // -----
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; CHECK: dlti.dl_spec =
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; CHECK: #dlti.dl_spec<
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; CHECK-DAG: "dlti.endianness" = "little"
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; CHECK-DAG: i64 = dense<64> : vector<2xi64>
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; CHECK-DAG: f80 = dense<128> : vector<2xi64>
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; CHECK-DAG: i8 = dense<8> : vector<2xi64>
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; CHECK-DAG: !llvm.ptr<270> = dense<[32, 64, 64, 32]> : vector<4xi64>
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; CHECK-DAG: !llvm.ptr<271> = dense<32> : vector<4xi64>
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; CHECK-DAG: !llvm.ptr<272> = dense<64> : vector<4xi64>
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; CHECK-DAG: "dlti.stack_alignment" = 128 : i64
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; CHECK-DAG: "dlti.mangling_mode" = "e"
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target datalayout = "e-m:e-p270:32:64-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
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; // -----
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; CHECK: dlti.dl_spec =
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; CHECK: #dlti.dl_spec<
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; CHECK-DAG: "dlti.endianness" = "big"
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; CHECK-DAG: !llvm.ptr<270> = dense<[16, 32, 64, 8]> : vector<4xi64>
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; CHECK-DAG: !llvm.ptr<271> = dense<[16, 32, 64, 16]> : vector<4xi64>
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; CHECK-DAG: "dlti.alloca_memory_space" = 1 : ui64
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; CHECK-DAG: i64 = dense<[64, 128]> : vector<2xi64>
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target datalayout = "A1-E-p270:16:32:64:8-p271:16:32:64-i64:64:128"
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; // -----
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; CHECK: dlti.dl_spec =
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; CHECK: #dlti.dl_spec<
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; CHECK-NOT: "dlti.alloca_memory_space" =
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target datalayout = "A0"
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