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llvm-project/llvm/lib/Target/RISCV
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Philip Reames 478cf94378 [X86][AArch64][WebAsm][RISCV] Query operand properties instead of using enums directly [nfc] 
This is part of an ongoing transition to use OperandValueInfo which combines OperandValueKind and OperandValueProperties.  This change adds some accessor methods and uses them to simplify backend code.  The primary motivation of doing so is removing uses of the parameters so that an upcoming api change is less error prone.
2022-08-22 13:37:59 -07:00
..
AsmParser
[RISCV] Implement support for the Zicbop extension
2022-06-28 12:43:26 +01:00
Disassembler
Rename MCFixedLenDisassembler.h as MCDecoderOps.h
2022-05-15 08:44:58 +08:00
MCTargetDesc
[RISCV] Change how mtune aliases are implemented.
2022-08-18 16:22:25 -07:00
TargetInfo
[RISCV] Re-enable JIT support
2022-08-11 11:41:02 +02:00
CMakeLists.txt
[RISCV] Add a RISCV specific CodeGenPrepare pass.
2022-07-14 10:20:59 -07:00
RISCV.h
[RISCV] Pre-RA expand pseudos pass
2022-07-31 23:19:00 +02:00
RISCV.td
[RISCV] Add zihintntl instructions
2022-08-22 12:06:30 +08:00
RISCVAsmPrinter.cpp
[CodeGen] Move instruction predicate verification to emitInstruction
2022-07-14 09:33:28 +01:00
RISCVCallingConv.td
…
RISCVCallLowering.cpp
…
RISCVCallLowering.h
…
RISCVCodeGenPrepare.cpp
[RISCV] isImpliedByDomCondition returns an Optional<bool> not a bool.
2022-08-12 22:21:05 -07:00
RISCVExpandAtomicPseudoInsts.cpp
[RISCV] Avoid redundant branch-to-branch when expanding cmpxchg
2022-08-17 13:49:15 +01:00
RISCVExpandPseudoInsts.cpp
[RISCV] Pre-RA expand pseudos pass
2022-07-31 23:19:00 +02:00
RISCVFrameLowering.cpp
Use llvm::none_of (NFC)
2022-08-14 16:25:39 -07:00
RISCVFrameLowering.h
[RISCV][NFCI] Set TransientStackAlignment and rely on it rather than RVV-specific logic on RVV-less functions
2022-08-02 09:46:06 +01:00
RISCVGatherScatterLowering.cpp
[RISCV] Don't require loop simplify form in RISCVGatherScatterLowering.
2022-06-10 13:00:20 -07:00
RISCVInsertVSETVLI.cpp
[RISCVInsertVSETVLI] Remove an unsound optimization
2022-08-05 12:13:08 -07:00
RISCVInstrFormats.td
[RISCV] Support mask policy for RVV IR intrinsics.
2022-03-22 01:19:16 -07:00
RISCVInstrFormatsC.td
…
RISCVInstrFormatsV.td
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RISCVInstrInfo.cpp
[RISCV][NFC] Use nested namespace definations.
2022-08-13 09:56:59 +08:00
RISCVInstrInfo.h
Remove redundaunt virtual specifiers (NFC)
2022-07-25 23:00:59 -07:00
RISCVInstrInfo.td
[RISCV] Add zihintntl instructions
2022-08-22 12:06:30 +08:00
RISCVInstrInfoA.td
[RISCV] Add target feature to force-enable atomics
2022-08-09 16:04:46 +02:00
RISCVInstrInfoC.td
[RISCV] Add MC support of RISCV Zca Extension
2022-08-18 12:13:35 +08:00
RISCVInstrInfoD.td
[RISCV] Explicitly select second operand of branch condition to X0.
2022-08-01 11:16:48 -07:00
RISCVInstrInfoF.td
[RISCV] Add ReadFStoreData as a SchedRead.
2022-08-08 09:33:19 -07:00
RISCVInstrInfoM.td
[RISCV][Clang] Add support for Zmmul extension
2022-07-18 20:26:08 -04:00
RISCVInstrInfoV.td
[RISCV] Add scheduling class for vector pseudo segment instructions.
2022-08-16 17:54:47 -07:00
RISCVInstrInfoVPseudos.td
[RISCV] Add scheduling class for vector pseudo segment instructions.
2022-08-16 17:54:47 -07:00
RISCVInstrInfoVSDPatterns.td
[RISCV] Increase complexity of RVV element extraction patterns
2022-07-11 10:53:15 +08:00
RISCVInstrInfoVVLPatterns.td
[RISCV] Add passthru operand to RISCVISD::SETCC_VL.
2022-08-19 08:53:44 -07:00
RISCVInstrInfoZb.td
[RISCV] Move xori creation for scalar setccs to lowering.
2022-08-19 13:51:53 -07:00
RISCVInstrInfoZfh.td
[RISCV] Explicitly select second operand of branch condition to X0.
2022-08-01 11:16:48 -07:00
RISCVInstrInfoZicbo.td
[RISCV] Implement support for the Zicbop extension
2022-06-28 12:43:26 +01:00
RISCVInstrInfoZk.td
[RISCV] Adjust some comments.
2022-02-01 22:53:54 +08:00
RISCVInstructionSelector.cpp
…
RISCVISelDAGToDAG.cpp
[RISCV] Copy SDNodeFlags in doPeepholeMaskedRVV and doPeepholeMergeVVMFold
2022-08-18 20:42:46 -07:00
RISCVISelDAGToDAG.h
[RISCV] Peephole optimization to fold merge.vvm and unmasked intrinsics.
2022-08-11 17:58:11 +08:00
RISCVISelLowering.cpp
[RISCV] Optimize x <s -1 ? x : -1. Improve x >u 1 ? x : 1.
2022-08-21 11:48:28 -07:00
RISCVISelLowering.h
[RISCV] Implement isUsedByReturnOnly TargetLowering hook in order to tailcall more libcalls
2022-08-10 10:50:29 +01:00
RISCVLegalizerInfo.cpp
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RISCVLegalizerInfo.h
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RISCVMachineFunctionInfo.cpp
llvm-reduce: Add cloning of target MachineFunctionInfo
2022-06-07 10:14:48 -04:00
RISCVMachineFunctionInfo.h
llvm-reduce: Add cloning of target MachineFunctionInfo
2022-06-07 10:14:48 -04:00
RISCVMacroFusion.cpp
[RISCV] Be more strict about LUI+ADDI macrofusion pre-RA.
2022-08-21 10:58:15 -07:00
RISCVMacroFusion.h
[RISCV] Add macrofusion infrastructure and one example usage.
2022-06-23 08:38:39 -07:00
RISCVMakeCompressible.cpp
[RISCV] Fix wrong register rename for store value during make-compressible optimization
2022-07-08 18:07:17 +08:00
RISCVMCInstLower.cpp
[RISCV] Pre-RA expand pseudos pass
2022-07-31 23:19:00 +02:00
RISCVMergeBaseOffset.cpp
[RISCV] Fix operand number in debug message in RISCVMergeBaseOffset.
2022-08-02 15:27:23 -07:00
RISCVRedundantCopyElimination.cpp
[RISCV] Remove impossible TODO in RISCVRedundantCopyElimination. NFC
2022-08-21 13:18:02 -07:00
RISCVRegisterBankInfo.cpp
[Target] Apply clang-tidy fixes for readability-redundant-member-init (NFC)
2022-03-27 22:22:37 -07:00
RISCVRegisterBankInfo.h
[nfc][codegen] Move RegisterBank[Info].h under CodeGen
2022-03-01 21:53:25 -08:00
RISCVRegisterBanks.td
…
RISCVRegisterInfo.cpp
[RISCV] Add a scavenge spill slot when use ADDI to compute scalable stack offset
2022-07-03 20:18:13 +08:00
RISCVRegisterInfo.h
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RISCVRegisterInfo.td
[RISCV] Add llvm.read.register support for vlenb
2022-05-13 09:12:02 -07:00
RISCVSchedRocket.td
[RISCV] Add ReadFStoreData as a SchedRead.
2022-08-08 09:33:19 -07:00
RISCVSchedSiFive7.td
[RISCV] Add ReadFStoreData as a SchedRead.
2022-08-08 09:33:19 -07:00
RISCVSchedule.td
[RISCV] Add ReadFStoreData as a SchedRead.
2022-08-08 09:33:19 -07:00
RISCVScheduleB.td
[RISCV] Add schedule class for Zbp extension and Zbr extension
2022-03-01 07:35:59 +00:00
RISCVScheduleV.td
[RISCV] Add scheduler class to PseudoReadVLENB.
2022-08-02 09:38:32 -07:00
RISCVSExtWRemoval.cpp
[llvm] LLVM_FALLTHROUGH => [[fallthrough]]. NFC
2022-08-08 11:24:15 -07:00
RISCVSubtarget.cpp
[RISCV] Disable subregister liveness by default
2022-07-14 17:04:10 +01:00
RISCVSubtarget.h
[RISCV] Add zihintntl instructions
2022-08-22 12:06:30 +08:00
RISCVSystemOperands.td
…
RISCVTargetMachine.cpp
[RISCV] Move Pre-RA pseudo expansion from addMachineSSAOptimization to addPreRegAlloc.
2022-08-01 13:44:43 -07:00
RISCVTargetMachine.h
[llvm] Remove redundaunt virtual specifiers (NFC)
2022-07-24 21:50:35 -07:00
RISCVTargetObjectFile.cpp
…
RISCVTargetObjectFile.h
…
RISCVTargetTransformInfo.cpp
[X86][AArch64][WebAsm][RISCV] Query operand properties instead of using enums directly [nfc]
2022-08-22 13:37:59 -07:00
RISCVTargetTransformInfo.h
[X86][AArch64][WebAsm][RISCV] Query operand properties instead of using enums directly [nfc]
2022-08-22 13:37:59 -07:00