llvm-project

History

[LV][VPlan] Reduce register usage of VPEVLBasedIVPHIRecipe. (#154482 )

`VPEVLBasedIVPHIRecipe` will lower to VPInstruction scalar phi and
generate scalar phi. This recipe will only occupy a scalar register just
like other phi recipes.

This patch fix the register usage for `VPEVLBasedIVPHIRecipe` from
vector
to scalar which is close to generated vector IR.

https://godbolt.org/z/6Mzd6W6ha shows that no register spills when
choosing `<vscale x 16>`.

Note that this test is basically copied from AArch64.

2025-08-21 07:39:01 +08:00

AggressiveInstCombine

Revert "[PatternMatch] Add m_[Shift]OrSelf matchers." (#152953 )

2025-08-11 09:35:16 +02:00

CFGuard

[x64][win] Add compiler support for x64 import call optimization (equivalent to MSVC /d2guardretpoline) (#126631 )

2025-05-20 14:48:41 -07:00

Coroutines

[coro] [async] Make sure to reprocess non-split async functions (#153419 )

2025-08-13 10:10:35 -07:00

HipStdPar

[HIPSTDPAR] Add handling for math builtins (#140158 )