b02b395a1e
The existing "LDS DMA" builtins/intrinsics copy data from global/buffer pointer to LDS. These are now augmented with their ".async" version, where the compiler does not automatically track completion. The completion is now tracked using explicit mark/wait intrinsics, which must be inserted by the user. This makes it possible to write programs with efficient waits in software pipeline loops. The program can now wait for only the oldest outstanding operations to finish, while launching more operations for later use. This change only contains the new names of the builtins/intrinsics, which continue to behave exactly like their non-async counterparts. A later change will implement the actual mark/wait semantics in SIInsertWaitcnts. This is part of a stack split out from #173259: - #180467 - #180466 Fixes: SWDEV-521121
701 lines
29 KiB
C++
701 lines
29 KiB
C++
//===------ SemaAMDGPU.cpp ------- AMDGPU target-specific routines --------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements semantic analysis functions specific to AMDGPU.
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//
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//===----------------------------------------------------------------------===//
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#include "clang/Sema/SemaAMDGPU.h"
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#include "clang/Basic/DiagnosticFrontend.h"
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#include "clang/Basic/DiagnosticSema.h"
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#include "clang/Basic/TargetBuiltins.h"
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#include "clang/Sema/Ownership.h"
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#include "clang/Sema/Sema.h"
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#include "llvm/Support/AMDGPUAddrSpace.h"
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#include "llvm/Support/AtomicOrdering.h"
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#include <cstdint>
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namespace clang {
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SemaAMDGPU::SemaAMDGPU(Sema &S) : SemaBase(S) {}
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bool SemaAMDGPU::CheckAMDGCNBuiltinFunctionCall(unsigned BuiltinID,
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CallExpr *TheCall) {
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// position of memory order and scope arguments in the builtin
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unsigned OrderIndex, ScopeIndex;
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const auto *FD = SemaRef.getCurFunctionDecl(/*AllowLambda=*/true);
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assert(FD && "AMDGPU builtins should not be used outside of a function");
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llvm::StringMap<bool> CallerFeatureMap;
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getASTContext().getFunctionFeatureMap(CallerFeatureMap, FD);
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bool HasGFX950Insts =
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Builtin::evaluateRequiredTargetFeatures("gfx950-insts", CallerFeatureMap);
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switch (BuiltinID) {
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case AMDGPU::BI__builtin_amdgcn_raw_ptr_buffer_load_lds:
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case AMDGPU::BI__builtin_amdgcn_raw_ptr_buffer_load_async_lds:
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case AMDGPU::BI__builtin_amdgcn_struct_ptr_buffer_load_lds:
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case AMDGPU::BI__builtin_amdgcn_struct_ptr_buffer_load_async_lds:
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case AMDGPU::BI__builtin_amdgcn_load_to_lds:
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case AMDGPU::BI__builtin_amdgcn_load_async_to_lds:
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case AMDGPU::BI__builtin_amdgcn_global_load_lds:
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case AMDGPU::BI__builtin_amdgcn_global_load_async_lds: {
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constexpr const int SizeIdx = 2;
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llvm::APSInt Size;
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Expr *ArgExpr = TheCall->getArg(SizeIdx);
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// Check for instantiation-dependent expressions (e.g., involving template
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// parameters). These will be checked again during template instantiation.
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if (ArgExpr->isInstantiationDependent())
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return false;
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[[maybe_unused]] ExprResult R =
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SemaRef.VerifyIntegerConstantExpression(ArgExpr, &Size);
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assert(!R.isInvalid());
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switch (Size.getSExtValue()) {
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case 1:
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case 2:
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case 4:
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return false;
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case 12:
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case 16: {
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if (HasGFX950Insts)
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return false;
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[[fallthrough]];
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}
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default:
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SemaRef.targetDiag(ArgExpr->getExprLoc(),
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diag::err_amdgcn_load_lds_size_invalid_value)
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<< ArgExpr->getSourceRange();
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SemaRef.targetDiag(ArgExpr->getExprLoc(),
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diag::note_amdgcn_load_lds_size_valid_value)
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<< HasGFX950Insts << ArgExpr->getSourceRange();
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return true;
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}
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}
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case AMDGPU::BI__builtin_amdgcn_get_fpenv:
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case AMDGPU::BI__builtin_amdgcn_set_fpenv:
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return false;
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case AMDGPU::BI__builtin_amdgcn_atomic_inc32:
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case AMDGPU::BI__builtin_amdgcn_atomic_inc64:
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case AMDGPU::BI__builtin_amdgcn_atomic_dec32:
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case AMDGPU::BI__builtin_amdgcn_atomic_dec64:
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OrderIndex = 2;
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ScopeIndex = 3;
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break;
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case AMDGPU::BI__builtin_amdgcn_fence:
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OrderIndex = 0;
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ScopeIndex = 1;
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break;
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case AMDGPU::BI__builtin_amdgcn_s_setreg:
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return SemaRef.BuiltinConstantArgRange(TheCall, /*ArgNum=*/0, /*Low=*/0,
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/*High=*/UINT16_MAX);
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case AMDGPU::BI__builtin_amdgcn_s_wait_event: {
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llvm::APSInt Result;
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if (SemaRef.BuiltinConstantArg(TheCall, 0, Result))
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return true;
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bool IsGFX12Plus = Builtin::evaluateRequiredTargetFeatures(
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"gfx12-insts", CallerFeatureMap);
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// gfx11 -> gfx12 changed the interpretation of the bitmask. gfx12 inverted
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// the intepretation for export_ready, but shifted the used bit by 1. Thus
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// waiting for the export_ready event can use a value of 2 universally.
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if (((IsGFX12Plus && !Result[1]) || (!IsGFX12Plus && Result[0])) ||
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Result.getZExtValue() > 2) {
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Expr *ArgExpr = TheCall->getArg(0);
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SemaRef.targetDiag(ArgExpr->getExprLoc(),
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diag::warn_amdgpu_s_wait_event_mask_no_effect_target)
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<< ArgExpr->getSourceRange();
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SemaRef.targetDiag(ArgExpr->getExprLoc(),
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diag::note_amdgpu_s_wait_event_suggested_value)
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<< ArgExpr->getSourceRange();
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}
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return false;
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}
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case AMDGPU::BI__builtin_amdgcn_mov_dpp:
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return checkMovDPPFunctionCall(TheCall, 5, 1);
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case AMDGPU::BI__builtin_amdgcn_mov_dpp8:
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return checkMovDPPFunctionCall(TheCall, 2, 1);
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case AMDGPU::BI__builtin_amdgcn_update_dpp:
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return checkMovDPPFunctionCall(TheCall, 6, 2);
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case AMDGPU::BI__builtin_amdgcn_cvt_scale_pk8_f16_fp8:
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case AMDGPU::BI__builtin_amdgcn_cvt_scale_pk8_bf16_fp8:
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case AMDGPU::BI__builtin_amdgcn_cvt_scale_pk8_f16_bf8:
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case AMDGPU::BI__builtin_amdgcn_cvt_scale_pk8_bf16_bf8:
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case AMDGPU::BI__builtin_amdgcn_cvt_scale_pk8_f16_fp4:
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case AMDGPU::BI__builtin_amdgcn_cvt_scale_pk8_bf16_fp4:
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case AMDGPU::BI__builtin_amdgcn_cvt_scale_pk8_f32_fp8:
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case AMDGPU::BI__builtin_amdgcn_cvt_scale_pk8_f32_bf8:
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case AMDGPU::BI__builtin_amdgcn_cvt_scale_pk8_f32_fp4:
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case AMDGPU::BI__builtin_amdgcn_cvt_scale_pk16_f16_fp6:
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case AMDGPU::BI__builtin_amdgcn_cvt_scale_pk16_bf16_fp6:
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case AMDGPU::BI__builtin_amdgcn_cvt_scale_pk16_f16_bf6:
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case AMDGPU::BI__builtin_amdgcn_cvt_scale_pk16_bf16_bf6:
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case AMDGPU::BI__builtin_amdgcn_cvt_scale_pk16_f32_fp6:
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case AMDGPU::BI__builtin_amdgcn_cvt_scale_pk16_f32_bf6:
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return SemaRef.BuiltinConstantArgRange(TheCall, 2, 0, 15);
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case AMDGPU::BI__builtin_amdgcn_cooperative_atomic_load_32x4B:
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case AMDGPU::BI__builtin_amdgcn_cooperative_atomic_load_16x8B:
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case AMDGPU::BI__builtin_amdgcn_cooperative_atomic_load_8x16B:
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return checkCoopAtomicFunctionCall(TheCall, /*IsStore=*/false);
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case AMDGPU::BI__builtin_amdgcn_cooperative_atomic_store_32x4B:
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case AMDGPU::BI__builtin_amdgcn_cooperative_atomic_store_16x8B:
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case AMDGPU::BI__builtin_amdgcn_cooperative_atomic_store_8x16B:
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return checkCoopAtomicFunctionCall(TheCall, /*IsStore=*/true);
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case AMDGPU::BI__builtin_amdgcn_flat_load_monitor_b32:
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case AMDGPU::BI__builtin_amdgcn_flat_load_monitor_b64:
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case AMDGPU::BI__builtin_amdgcn_flat_load_monitor_b128:
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case AMDGPU::BI__builtin_amdgcn_global_load_monitor_b32:
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case AMDGPU::BI__builtin_amdgcn_global_load_monitor_b64:
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case AMDGPU::BI__builtin_amdgcn_global_load_monitor_b128:
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return checkAtomicMonitorLoad(TheCall);
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case AMDGPU::BI__builtin_amdgcn_image_load_1d_v4f32_i32:
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case AMDGPU::BI__builtin_amdgcn_image_load_1darray_v4f32_i32:
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case AMDGPU::BI__builtin_amdgcn_image_load_1d_v4f16_i32:
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case AMDGPU::BI__builtin_amdgcn_image_load_1darray_v4f16_i32:
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case AMDGPU::BI__builtin_amdgcn_image_load_2d_f32_i32:
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case AMDGPU::BI__builtin_amdgcn_image_load_2d_v4f32_i32:
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case AMDGPU::BI__builtin_amdgcn_image_load_2d_v4f16_i32:
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case AMDGPU::BI__builtin_amdgcn_image_load_2darray_f32_i32:
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case AMDGPU::BI__builtin_amdgcn_image_load_2darray_v4f32_i32:
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case AMDGPU::BI__builtin_amdgcn_image_load_2darray_v4f16_i32:
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case AMDGPU::BI__builtin_amdgcn_image_load_3d_v4f32_i32:
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case AMDGPU::BI__builtin_amdgcn_image_load_3d_v4f16_i32:
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case AMDGPU::BI__builtin_amdgcn_image_load_cube_v4f32_i32:
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case AMDGPU::BI__builtin_amdgcn_image_load_cube_v4f16_i32:
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case AMDGPU::BI__builtin_amdgcn_image_load_mip_1d_v4f32_i32:
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case AMDGPU::BI__builtin_amdgcn_image_load_mip_1d_v4f16_i32:
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case AMDGPU::BI__builtin_amdgcn_image_load_mip_1darray_v4f32_i32:
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case AMDGPU::BI__builtin_amdgcn_image_load_mip_1darray_v4f16_i32:
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case AMDGPU::BI__builtin_amdgcn_image_load_mip_2d_f32_i32:
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case AMDGPU::BI__builtin_amdgcn_image_load_mip_2d_v4f32_i32:
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case AMDGPU::BI__builtin_amdgcn_image_load_mip_2d_v4f16_i32:
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case AMDGPU::BI__builtin_amdgcn_image_load_mip_2darray_f32_i32:
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case AMDGPU::BI__builtin_amdgcn_image_load_mip_2darray_v4f32_i32:
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case AMDGPU::BI__builtin_amdgcn_image_load_mip_2darray_v4f16_i32:
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case AMDGPU::BI__builtin_amdgcn_image_load_mip_3d_v4f32_i32:
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case AMDGPU::BI__builtin_amdgcn_image_load_mip_3d_v4f16_i32:
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case AMDGPU::BI__builtin_amdgcn_image_load_mip_cube_v4f32_i32:
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case AMDGPU::BI__builtin_amdgcn_image_load_mip_cube_v4f16_i32:
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case AMDGPU::BI__builtin_amdgcn_image_sample_1d_v4f32_f32:
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case AMDGPU::BI__builtin_amdgcn_image_sample_1darray_v4f32_f32:
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case AMDGPU::BI__builtin_amdgcn_image_sample_1d_v4f16_f32:
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case AMDGPU::BI__builtin_amdgcn_image_sample_1darray_v4f16_f32:
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case AMDGPU::BI__builtin_amdgcn_image_sample_2d_f32_f32:
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case AMDGPU::BI__builtin_amdgcn_image_sample_2d_v4f32_f32:
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case AMDGPU::BI__builtin_amdgcn_image_sample_2d_v4f16_f32:
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case AMDGPU::BI__builtin_amdgcn_image_sample_2darray_f32_f32:
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case AMDGPU::BI__builtin_amdgcn_image_sample_2darray_v4f32_f32:
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case AMDGPU::BI__builtin_amdgcn_image_sample_2darray_v4f16_f32:
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case AMDGPU::BI__builtin_amdgcn_image_sample_3d_v4f32_f32:
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case AMDGPU::BI__builtin_amdgcn_image_sample_3d_v4f16_f32:
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case AMDGPU::BI__builtin_amdgcn_image_sample_cube_v4f32_f32:
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case AMDGPU::BI__builtin_amdgcn_image_sample_cube_v4f16_f32:
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case AMDGPU::BI__builtin_amdgcn_image_sample_lz_1d_v4f32_f32:
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case AMDGPU::BI__builtin_amdgcn_image_sample_lz_1d_v4f16_f32:
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case AMDGPU::BI__builtin_amdgcn_image_sample_lz_1darray_v4f32_f32:
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case AMDGPU::BI__builtin_amdgcn_image_sample_lz_1darray_v4f16_f32:
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case AMDGPU::BI__builtin_amdgcn_image_sample_lz_2d_f32_f32:
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case AMDGPU::BI__builtin_amdgcn_image_sample_lz_2d_v4f32_f32:
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case AMDGPU::BI__builtin_amdgcn_image_sample_lz_2d_v4f16_f32:
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case AMDGPU::BI__builtin_amdgcn_image_sample_lz_2darray_f32_f32:
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case AMDGPU::BI__builtin_amdgcn_image_sample_lz_2darray_v4f32_f32:
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case AMDGPU::BI__builtin_amdgcn_image_sample_lz_2darray_v4f16_f32:
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case AMDGPU::BI__builtin_amdgcn_image_sample_lz_3d_v4f32_f32:
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case AMDGPU::BI__builtin_amdgcn_image_sample_lz_3d_v4f16_f32:
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case AMDGPU::BI__builtin_amdgcn_image_sample_lz_cube_v4f32_f32:
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case AMDGPU::BI__builtin_amdgcn_image_sample_lz_cube_v4f16_f32:
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case AMDGPU::BI__builtin_amdgcn_image_sample_l_1d_v4f32_f32:
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case AMDGPU::BI__builtin_amdgcn_image_sample_l_1d_v4f16_f32:
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case AMDGPU::BI__builtin_amdgcn_image_sample_l_1darray_v4f32_f32:
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case AMDGPU::BI__builtin_amdgcn_image_sample_l_1darray_v4f16_f32:
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case AMDGPU::BI__builtin_amdgcn_image_sample_l_2d_f32_f32:
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case AMDGPU::BI__builtin_amdgcn_image_sample_l_2d_v4f16_f32:
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case AMDGPU::BI__builtin_amdgcn_image_sample_l_2d_v4f32_f32:
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case AMDGPU::BI__builtin_amdgcn_image_sample_l_2darray_f32_f32:
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case AMDGPU::BI__builtin_amdgcn_image_sample_l_2darray_v4f32_f32:
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case AMDGPU::BI__builtin_amdgcn_image_sample_l_2darray_v4f16_f32:
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case AMDGPU::BI__builtin_amdgcn_image_sample_l_3d_v4f32_f32:
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case AMDGPU::BI__builtin_amdgcn_image_sample_l_3d_v4f16_f32:
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case AMDGPU::BI__builtin_amdgcn_image_sample_l_cube_v4f32_f32:
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case AMDGPU::BI__builtin_amdgcn_image_sample_l_cube_v4f16_f32:
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case AMDGPU::BI__builtin_amdgcn_image_sample_d_1d_v4f32_f32:
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case AMDGPU::BI__builtin_amdgcn_image_sample_d_1d_v4f16_f32:
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case AMDGPU::BI__builtin_amdgcn_image_sample_d_1darray_v4f32_f32:
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case AMDGPU::BI__builtin_amdgcn_image_sample_d_1darray_v4f16_f32:
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case AMDGPU::BI__builtin_amdgcn_image_sample_d_2d_f32_f32:
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case AMDGPU::BI__builtin_amdgcn_image_sample_d_2d_v4f32_f32:
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case AMDGPU::BI__builtin_amdgcn_image_sample_d_2d_v4f16_f32:
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case AMDGPU::BI__builtin_amdgcn_image_sample_d_2darray_f32_f32:
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case AMDGPU::BI__builtin_amdgcn_image_sample_d_2darray_v4f32_f32:
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case AMDGPU::BI__builtin_amdgcn_image_sample_d_2darray_v4f16_f32:
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case AMDGPU::BI__builtin_amdgcn_image_sample_d_3d_v4f32_f32:
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case AMDGPU::BI__builtin_amdgcn_image_sample_d_3d_v4f16_f32:
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case AMDGPU::BI__builtin_amdgcn_image_gather4_lz_2d_v4f32_f32: {
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StringRef FeatureList(
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getASTContext().BuiltinInfo.getRequiredFeatures(BuiltinID));
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if (!Builtin::evaluateRequiredTargetFeatures(FeatureList,
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CallerFeatureMap)) {
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Diag(TheCall->getBeginLoc(), diag::err_builtin_needs_feature)
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<< FD->getDeclName() << FeatureList;
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return false;
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}
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unsigned ArgCount = TheCall->getNumArgs() - 1;
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llvm::APSInt Result;
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return (SemaRef.BuiltinConstantArg(TheCall, 0, Result)) ||
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(SemaRef.BuiltinConstantArg(TheCall, ArgCount, Result)) ||
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(SemaRef.BuiltinConstantArg(TheCall, (ArgCount - 1), Result));
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}
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case AMDGPU::BI__builtin_amdgcn_image_store_1d_v4f32_i32:
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case AMDGPU::BI__builtin_amdgcn_image_store_1darray_v4f32_i32:
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case AMDGPU::BI__builtin_amdgcn_image_store_1d_v4f16_i32:
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case AMDGPU::BI__builtin_amdgcn_image_store_1darray_v4f16_i32:
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case AMDGPU::BI__builtin_amdgcn_image_store_2d_f32_i32:
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case AMDGPU::BI__builtin_amdgcn_image_store_2d_v4f32_i32:
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case AMDGPU::BI__builtin_amdgcn_image_store_2d_v4f16_i32:
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case AMDGPU::BI__builtin_amdgcn_image_store_2darray_f32_i32:
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case AMDGPU::BI__builtin_amdgcn_image_store_2darray_v4f32_i32:
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case AMDGPU::BI__builtin_amdgcn_image_store_2darray_v4f16_i32:
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case AMDGPU::BI__builtin_amdgcn_image_store_3d_v4f32_i32:
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case AMDGPU::BI__builtin_amdgcn_image_store_3d_v4f16_i32:
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case AMDGPU::BI__builtin_amdgcn_image_store_cube_v4f32_i32:
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case AMDGPU::BI__builtin_amdgcn_image_store_cube_v4f16_i32:
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case AMDGPU::BI__builtin_amdgcn_image_store_mip_1d_v4f32_i32:
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case AMDGPU::BI__builtin_amdgcn_image_store_mip_1d_v4f16_i32:
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case AMDGPU::BI__builtin_amdgcn_image_store_mip_1darray_v4f32_i32:
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case AMDGPU::BI__builtin_amdgcn_image_store_mip_1darray_v4f16_i32:
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case AMDGPU::BI__builtin_amdgcn_image_store_mip_2d_f32_i32:
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case AMDGPU::BI__builtin_amdgcn_image_store_mip_2d_v4f32_i32:
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case AMDGPU::BI__builtin_amdgcn_image_store_mip_2d_v4f16_i32:
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case AMDGPU::BI__builtin_amdgcn_image_store_mip_2darray_f32_i32:
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case AMDGPU::BI__builtin_amdgcn_image_store_mip_2darray_v4f32_i32:
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case AMDGPU::BI__builtin_amdgcn_image_store_mip_2darray_v4f16_i32:
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case AMDGPU::BI__builtin_amdgcn_image_store_mip_3d_v4f32_i32:
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case AMDGPU::BI__builtin_amdgcn_image_store_mip_3d_v4f16_i32:
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case AMDGPU::BI__builtin_amdgcn_image_store_mip_cube_v4f32_i32:
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case AMDGPU::BI__builtin_amdgcn_image_store_mip_cube_v4f16_i32: {
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StringRef FeatureList(
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getASTContext().BuiltinInfo.getRequiredFeatures(BuiltinID));
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if (!Builtin::evaluateRequiredTargetFeatures(FeatureList,
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CallerFeatureMap)) {
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Diag(TheCall->getBeginLoc(), diag::err_builtin_needs_feature)
|
|
<< FD->getDeclName() << FeatureList;
|
|
return false;
|
|
}
|
|
|
|
unsigned ArgCount = TheCall->getNumArgs() - 1;
|
|
llvm::APSInt Result;
|
|
|
|
return (SemaRef.BuiltinConstantArg(TheCall, 1, Result)) ||
|
|
(SemaRef.BuiltinConstantArg(TheCall, ArgCount, Result)) ||
|
|
(SemaRef.BuiltinConstantArg(TheCall, (ArgCount - 1), Result));
|
|
}
|
|
case AMDGPU::BI__builtin_amdgcn_wmma_i32_16x16x64_iu8:
|
|
case AMDGPU::BI__builtin_amdgcn_swmmac_i32_16x16x128_iu8: {
|
|
if (BuiltinID == AMDGPU::BI__builtin_amdgcn_wmma_i32_16x16x64_iu8) {
|
|
if (SemaRef.checkArgCountRange(TheCall, 7, 8))
|
|
return true;
|
|
if (TheCall->getNumArgs() == 7)
|
|
return false;
|
|
} else if (BuiltinID ==
|
|
AMDGPU::BI__builtin_amdgcn_swmmac_i32_16x16x128_iu8) {
|
|
if (SemaRef.checkArgCountRange(TheCall, 8, 9))
|
|
return true;
|
|
if (TheCall->getNumArgs() == 8)
|
|
return false;
|
|
}
|
|
// Check if the last argument (clamp operand) is a constant and is
|
|
// convertible to bool.
|
|
Expr *ClampArg = TheCall->getArg(TheCall->getNumArgs() - 1);
|
|
// 1) Ensure clamp argument is a constant expression
|
|
llvm::APSInt ClampValue;
|
|
if (!SemaRef.VerifyIntegerConstantExpression(ClampArg, &ClampValue)
|
|
.isUsable())
|
|
return true;
|
|
// 2) Check if the argument can be converted to bool type
|
|
if (!SemaRef.Context.hasSameType(ClampArg->getType(),
|
|
SemaRef.Context.BoolTy)) {
|
|
// Try to convert to bool
|
|
QualType BoolTy = SemaRef.Context.BoolTy;
|
|
ExprResult ClampExpr(ClampArg);
|
|
SemaRef.CheckSingleAssignmentConstraints(BoolTy, ClampExpr);
|
|
if (ClampExpr.isInvalid())
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
default:
|
|
return false;
|
|
}
|
|
|
|
ExprResult Arg = TheCall->getArg(OrderIndex);
|
|
auto ArgExpr = Arg.get();
|
|
Expr::EvalResult ArgResult;
|
|
|
|
if (!ArgExpr->EvaluateAsInt(ArgResult, getASTContext()))
|
|
return Diag(ArgExpr->getExprLoc(), diag::err_typecheck_expect_int)
|
|
<< ArgExpr->getType();
|
|
auto Ord = ArgResult.Val.getInt().getZExtValue();
|
|
|
|
// Check validity of memory ordering as per C11 / C++11's memory model.
|
|
// Only fence needs check. Atomic dec/inc allow all memory orders.
|
|
if (!llvm::isValidAtomicOrderingCABI(Ord))
|
|
return Diag(ArgExpr->getBeginLoc(),
|
|
diag::warn_atomic_op_has_invalid_memory_order)
|
|
<< 0 << ArgExpr->getSourceRange();
|
|
switch (static_cast<llvm::AtomicOrderingCABI>(Ord)) {
|
|
case llvm::AtomicOrderingCABI::relaxed:
|
|
case llvm::AtomicOrderingCABI::consume:
|
|
if (BuiltinID == AMDGPU::BI__builtin_amdgcn_fence)
|
|
return Diag(ArgExpr->getBeginLoc(),
|
|
diag::warn_atomic_op_has_invalid_memory_order)
|
|
<< 0 << ArgExpr->getSourceRange();
|
|
break;
|
|
case llvm::AtomicOrderingCABI::acquire:
|
|
case llvm::AtomicOrderingCABI::release:
|
|
case llvm::AtomicOrderingCABI::acq_rel:
|
|
case llvm::AtomicOrderingCABI::seq_cst:
|
|
break;
|
|
}
|
|
|
|
Arg = TheCall->getArg(ScopeIndex);
|
|
ArgExpr = Arg.get();
|
|
Expr::EvalResult ArgResult1;
|
|
// Check that sync scope is a constant literal
|
|
if (!ArgExpr->EvaluateAsConstantExpr(ArgResult1, getASTContext()))
|
|
return Diag(ArgExpr->getExprLoc(), diag::err_expr_not_string_literal)
|
|
<< ArgExpr->getType();
|
|
|
|
return false;
|
|
}
|
|
|
|
bool SemaAMDGPU::checkAtomicOrderingCABIArg(Expr *E, bool MayLoad,
|
|
bool MayStore) {
|
|
Expr::EvalResult AtomicOrdArgRes;
|
|
if (!E->EvaluateAsInt(AtomicOrdArgRes, getASTContext()))
|
|
llvm_unreachable("Intrinsic requires imm for atomic ordering argument!");
|
|
auto Ord =
|
|
llvm::AtomicOrderingCABI(AtomicOrdArgRes.Val.getInt().getZExtValue());
|
|
|
|
// Atomic ordering cannot be acq_rel in any case, acquire for stores or
|
|
// release for loads.
|
|
if (!llvm::isValidAtomicOrderingCABI((unsigned)Ord) ||
|
|
(!(MayLoad && MayStore) && (Ord == llvm::AtomicOrderingCABI::acq_rel)) ||
|
|
(!MayLoad && Ord == llvm::AtomicOrderingCABI::acquire) ||
|
|
(!MayStore && Ord == llvm::AtomicOrderingCABI::release)) {
|
|
return Diag(E->getBeginLoc(), diag::warn_atomic_op_has_invalid_memory_order)
|
|
<< 0 << E->getSourceRange();
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
bool SemaAMDGPU::checkCoopAtomicFunctionCall(CallExpr *TheCall, bool IsStore) {
|
|
bool Fail = false;
|
|
|
|
// First argument is a global or generic pointer.
|
|
Expr *PtrArg = TheCall->getArg(0);
|
|
QualType PtrTy = PtrArg->getType()->getPointeeType();
|
|
unsigned AS = getASTContext().getTargetAddressSpace(PtrTy.getAddressSpace());
|
|
if (AS != llvm::AMDGPUAS::FLAT_ADDRESS &&
|
|
AS != llvm::AMDGPUAS::GLOBAL_ADDRESS) {
|
|
Fail = true;
|
|
Diag(TheCall->getBeginLoc(), diag::err_amdgcn_coop_atomic_invalid_as)
|
|
<< PtrArg->getSourceRange();
|
|
}
|
|
|
|
Expr *AO = TheCall->getArg(IsStore ? 2 : 1);
|
|
Expr *Scope = TheCall->getArg(TheCall->getNumArgs() - 1);
|
|
|
|
if (AO->isValueDependent() || Scope->isValueDependent())
|
|
return false;
|
|
|
|
// Check atomic ordering
|
|
Fail |=
|
|
checkAtomicOrderingCABIArg(TheCall->getArg(IsStore ? 2 : 1),
|
|
/*MayLoad=*/!IsStore, /*MayStore=*/IsStore);
|
|
|
|
// Last argument is the syncscope as a string literal.
|
|
if (!isa<StringLiteral>(Scope->IgnoreParenImpCasts())) {
|
|
Diag(TheCall->getBeginLoc(), diag::err_expr_not_string_literal)
|
|
<< Scope->getSourceRange();
|
|
Fail = true;
|
|
}
|
|
|
|
return Fail;
|
|
}
|
|
|
|
bool SemaAMDGPU::checkAtomicMonitorLoad(CallExpr *TheCall) {
|
|
bool Fail = false;
|
|
|
|
Expr *AO = TheCall->getArg(1);
|
|
Expr *Scope = TheCall->getArg(TheCall->getNumArgs() - 1);
|
|
|
|
if (AO->isValueDependent() || Scope->isValueDependent())
|
|
return false;
|
|
|
|
Fail |= checkAtomicOrderingCABIArg(TheCall->getArg(1), /*MayLoad=*/true,
|
|
/*MayStore=*/false);
|
|
|
|
auto ScopeModel = AtomicScopeModel::create(AtomicScopeModelKind::Generic);
|
|
if (std::optional<llvm::APSInt> Result =
|
|
Scope->getIntegerConstantExpr(SemaRef.Context)) {
|
|
if (!ScopeModel->isValid(Result->getZExtValue())) {
|
|
Diag(Scope->getBeginLoc(), diag::err_atomic_op_has_invalid_sync_scope)
|
|
<< Scope->getSourceRange();
|
|
Fail = true;
|
|
}
|
|
}
|
|
|
|
return Fail;
|
|
}
|
|
|
|
bool SemaAMDGPU::checkMovDPPFunctionCall(CallExpr *TheCall, unsigned NumArgs,
|
|
unsigned NumDataArgs) {
|
|
assert(NumDataArgs <= 2);
|
|
if (SemaRef.checkArgCountRange(TheCall, NumArgs, NumArgs))
|
|
return true;
|
|
Expr *Args[2];
|
|
QualType ArgTys[2];
|
|
for (unsigned I = 0; I != NumDataArgs; ++I) {
|
|
Args[I] = TheCall->getArg(I);
|
|
ArgTys[I] = Args[I]->getType();
|
|
// TODO: Vectors can also be supported.
|
|
if (!ArgTys[I]->isArithmeticType() || ArgTys[I]->isAnyComplexType()) {
|
|
SemaRef.Diag(Args[I]->getBeginLoc(),
|
|
diag::err_typecheck_cond_expect_int_float)
|
|
<< ArgTys[I] << Args[I]->getSourceRange();
|
|
return true;
|
|
}
|
|
}
|
|
if (NumDataArgs < 2)
|
|
return false;
|
|
|
|
if (getASTContext().hasSameUnqualifiedType(ArgTys[0], ArgTys[1]))
|
|
return false;
|
|
|
|
if (((ArgTys[0]->isUnsignedIntegerType() &&
|
|
ArgTys[1]->isSignedIntegerType()) ||
|
|
(ArgTys[0]->isSignedIntegerType() &&
|
|
ArgTys[1]->isUnsignedIntegerType())) &&
|
|
getASTContext().getTypeSize(ArgTys[0]) ==
|
|
getASTContext().getTypeSize(ArgTys[1]))
|
|
return false;
|
|
|
|
SemaRef.Diag(Args[1]->getBeginLoc(),
|
|
diag::err_typecheck_call_different_arg_types)
|
|
<< ArgTys[0] << ArgTys[1];
|
|
return true;
|
|
}
|
|
|
|
static bool
|
|
checkAMDGPUFlatWorkGroupSizeArguments(Sema &S, Expr *MinExpr, Expr *MaxExpr,
|
|
const AMDGPUFlatWorkGroupSizeAttr &Attr) {
|
|
// Accept template arguments for now as they depend on something else.
|
|
// We'll get to check them when they eventually get instantiated.
|
|
if (MinExpr->isValueDependent() || MaxExpr->isValueDependent())
|
|
return false;
|
|
|
|
uint32_t Min = 0;
|
|
if (!S.checkUInt32Argument(Attr, MinExpr, Min, 0))
|
|
return true;
|
|
|
|
uint32_t Max = 0;
|
|
if (!S.checkUInt32Argument(Attr, MaxExpr, Max, 1))
|
|
return true;
|
|
|
|
if (Min == 0 && Max != 0) {
|
|
S.Diag(Attr.getLocation(), diag::err_attribute_argument_invalid)
|
|
<< &Attr << 0;
|
|
return true;
|
|
}
|
|
if (Min > Max) {
|
|
S.Diag(Attr.getLocation(), diag::err_attribute_argument_invalid)
|
|
<< &Attr << 1;
|
|
return true;
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
AMDGPUFlatWorkGroupSizeAttr *
|
|
SemaAMDGPU::CreateAMDGPUFlatWorkGroupSizeAttr(const AttributeCommonInfo &CI,
|
|
Expr *MinExpr, Expr *MaxExpr) {
|
|
ASTContext &Context = getASTContext();
|
|
AMDGPUFlatWorkGroupSizeAttr TmpAttr(Context, CI, MinExpr, MaxExpr);
|
|
|
|
if (checkAMDGPUFlatWorkGroupSizeArguments(SemaRef, MinExpr, MaxExpr, TmpAttr))
|
|
return nullptr;
|
|
return ::new (Context)
|
|
AMDGPUFlatWorkGroupSizeAttr(Context, CI, MinExpr, MaxExpr);
|
|
}
|
|
|
|
void SemaAMDGPU::addAMDGPUFlatWorkGroupSizeAttr(Decl *D,
|
|
const AttributeCommonInfo &CI,
|
|
Expr *MinExpr, Expr *MaxExpr) {
|
|
if (auto *Attr = CreateAMDGPUFlatWorkGroupSizeAttr(CI, MinExpr, MaxExpr))
|
|
D->addAttr(Attr);
|
|
}
|
|
|
|
void SemaAMDGPU::handleAMDGPUFlatWorkGroupSizeAttr(Decl *D,
|
|
const ParsedAttr &AL) {
|
|
Expr *MinExpr = AL.getArgAsExpr(0);
|
|
Expr *MaxExpr = AL.getArgAsExpr(1);
|
|
|
|
addAMDGPUFlatWorkGroupSizeAttr(D, AL, MinExpr, MaxExpr);
|
|
}
|
|
|
|
static bool checkAMDGPUWavesPerEUArguments(Sema &S, Expr *MinExpr,
|
|
Expr *MaxExpr,
|
|
const AMDGPUWavesPerEUAttr &Attr) {
|
|
if (S.DiagnoseUnexpandedParameterPack(MinExpr) ||
|
|
(MaxExpr && S.DiagnoseUnexpandedParameterPack(MaxExpr)))
|
|
return true;
|
|
|
|
// Accept template arguments for now as they depend on something else.
|
|
// We'll get to check them when they eventually get instantiated.
|
|
if (MinExpr->isValueDependent() || (MaxExpr && MaxExpr->isValueDependent()))
|
|
return false;
|
|
|
|
uint32_t Min = 0;
|
|
if (!S.checkUInt32Argument(Attr, MinExpr, Min, 0))
|
|
return true;
|
|
|
|
uint32_t Max = 0;
|
|
if (MaxExpr && !S.checkUInt32Argument(Attr, MaxExpr, Max, 1))
|
|
return true;
|
|
|
|
if (Min == 0 && Max != 0) {
|
|
S.Diag(Attr.getLocation(), diag::err_attribute_argument_invalid)
|
|
<< &Attr << 0;
|
|
return true;
|
|
}
|
|
if (Max != 0 && Min > Max) {
|
|
S.Diag(Attr.getLocation(), diag::err_attribute_argument_invalid)
|
|
<< &Attr << 1;
|
|
return true;
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
AMDGPUWavesPerEUAttr *
|
|
SemaAMDGPU::CreateAMDGPUWavesPerEUAttr(const AttributeCommonInfo &CI,
|
|
Expr *MinExpr, Expr *MaxExpr) {
|
|
ASTContext &Context = getASTContext();
|
|
AMDGPUWavesPerEUAttr TmpAttr(Context, CI, MinExpr, MaxExpr);
|
|
|
|
if (checkAMDGPUWavesPerEUArguments(SemaRef, MinExpr, MaxExpr, TmpAttr))
|
|
return nullptr;
|
|
|
|
return ::new (Context) AMDGPUWavesPerEUAttr(Context, CI, MinExpr, MaxExpr);
|
|
}
|
|
|
|
void SemaAMDGPU::addAMDGPUWavesPerEUAttr(Decl *D, const AttributeCommonInfo &CI,
|
|
Expr *MinExpr, Expr *MaxExpr) {
|
|
if (auto *Attr = CreateAMDGPUWavesPerEUAttr(CI, MinExpr, MaxExpr))
|
|
D->addAttr(Attr);
|
|
}
|
|
|
|
void SemaAMDGPU::handleAMDGPUWavesPerEUAttr(Decl *D, const ParsedAttr &AL) {
|
|
if (!AL.checkAtLeastNumArgs(SemaRef, 1) || !AL.checkAtMostNumArgs(SemaRef, 2))
|
|
return;
|
|
|
|
Expr *MinExpr = AL.getArgAsExpr(0);
|
|
Expr *MaxExpr = (AL.getNumArgs() > 1) ? AL.getArgAsExpr(1) : nullptr;
|
|
|
|
addAMDGPUWavesPerEUAttr(D, AL, MinExpr, MaxExpr);
|
|
}
|
|
|
|
void SemaAMDGPU::handleAMDGPUNumSGPRAttr(Decl *D, const ParsedAttr &AL) {
|
|
uint32_t NumSGPR = 0;
|
|
Expr *NumSGPRExpr = AL.getArgAsExpr(0);
|
|
if (!SemaRef.checkUInt32Argument(AL, NumSGPRExpr, NumSGPR))
|
|
return;
|
|
|
|
D->addAttr(::new (getASTContext())
|
|
AMDGPUNumSGPRAttr(getASTContext(), AL, NumSGPR));
|
|
}
|
|
|
|
void SemaAMDGPU::handleAMDGPUNumVGPRAttr(Decl *D, const ParsedAttr &AL) {
|
|
uint32_t NumVGPR = 0;
|
|
Expr *NumVGPRExpr = AL.getArgAsExpr(0);
|
|
if (!SemaRef.checkUInt32Argument(AL, NumVGPRExpr, NumVGPR))
|
|
return;
|
|
|
|
D->addAttr(::new (getASTContext())
|
|
AMDGPUNumVGPRAttr(getASTContext(), AL, NumVGPR));
|
|
}
|
|
|
|
static bool
|
|
checkAMDGPUMaxNumWorkGroupsArguments(Sema &S, Expr *XExpr, Expr *YExpr,
|
|
Expr *ZExpr,
|
|
const AMDGPUMaxNumWorkGroupsAttr &Attr) {
|
|
if (S.DiagnoseUnexpandedParameterPack(XExpr) ||
|
|
(YExpr && S.DiagnoseUnexpandedParameterPack(YExpr)) ||
|
|
(ZExpr && S.DiagnoseUnexpandedParameterPack(ZExpr)))
|
|
return true;
|
|
|
|
// Accept template arguments for now as they depend on something else.
|
|
// We'll get to check them when they eventually get instantiated.
|
|
if (XExpr->isValueDependent() || (YExpr && YExpr->isValueDependent()) ||
|
|
(ZExpr && ZExpr->isValueDependent()))
|
|
return false;
|
|
|
|
uint32_t NumWG = 0;
|
|
Expr *Exprs[3] = {XExpr, YExpr, ZExpr};
|
|
for (int i = 0; i < 3; i++) {
|
|
if (Exprs[i]) {
|
|
if (!S.checkUInt32Argument(Attr, Exprs[i], NumWG, i,
|
|
/*StrictlyUnsigned=*/true))
|
|
return true;
|
|
if (NumWG == 0) {
|
|
S.Diag(Attr.getLoc(), diag::err_attribute_argument_is_zero)
|
|
<< &Attr << Exprs[i]->getSourceRange();
|
|
return true;
|
|
}
|
|
}
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
AMDGPUMaxNumWorkGroupsAttr *SemaAMDGPU::CreateAMDGPUMaxNumWorkGroupsAttr(
|
|
const AttributeCommonInfo &CI, Expr *XExpr, Expr *YExpr, Expr *ZExpr) {
|
|
ASTContext &Context = getASTContext();
|
|
AMDGPUMaxNumWorkGroupsAttr TmpAttr(Context, CI, XExpr, YExpr, ZExpr);
|
|
assert(!SemaRef.isSFINAEContext() &&
|
|
"Can't produce SFINAE diagnostic pointing to temporary attribute");
|
|
|
|
if (checkAMDGPUMaxNumWorkGroupsArguments(SemaRef, XExpr, YExpr, ZExpr,
|
|
TmpAttr))
|
|
return nullptr;
|
|
|
|
return ::new (Context)
|
|
AMDGPUMaxNumWorkGroupsAttr(Context, CI, XExpr, YExpr, ZExpr);
|
|
}
|
|
|
|
void SemaAMDGPU::addAMDGPUMaxNumWorkGroupsAttr(Decl *D,
|
|
const AttributeCommonInfo &CI,
|
|
Expr *XExpr, Expr *YExpr,
|
|
Expr *ZExpr) {
|
|
if (auto *Attr = CreateAMDGPUMaxNumWorkGroupsAttr(CI, XExpr, YExpr, ZExpr))
|
|
D->addAttr(Attr);
|
|
}
|
|
|
|
void SemaAMDGPU::handleAMDGPUMaxNumWorkGroupsAttr(Decl *D,
|
|
const ParsedAttr &AL) {
|
|
Expr *YExpr = (AL.getNumArgs() > 1) ? AL.getArgAsExpr(1) : nullptr;
|
|
Expr *ZExpr = (AL.getNumArgs() > 2) ? AL.getArgAsExpr(2) : nullptr;
|
|
addAMDGPUMaxNumWorkGroupsAttr(D, AL, AL.getArgAsExpr(0), YExpr, ZExpr);
|
|
}
|
|
|
|
} // namespace clang
|