369891b674
In most cases, the type information attached to load and store instructions is meaningless and inconsistently applied. We can usually use ".b" loads and avoid the complexity of trying to assign the correct type. The one expectation is sign-extending load, which will continue to use ".s" to ensure the sign extension into a larger register is done correctly.
299 lines
12 KiB
Plaintext
299 lines
12 KiB
Plaintext
// REQUIRES: x86-registered-target, nvptx-registered-target, amdgpu-registered-target
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// By default CUDA uses -ffp-contract=fast, HIP uses -ffp-contract=fast-honor-pragmas.
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// we should fuse multiply/add into fma instruction.
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// In IR, fmul/fadd instructions with contract flag are emitted.
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// In backend
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// nvptx - assumes fast fp fuse option, which fuses
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// mult/add insts disregarding contract flag and
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// llvm.fmuladd intrinsics.
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// amdgcn - assumes standard fp fuse option, which only
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// fuses mult/add insts with contract flag and
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// llvm.fmuladd intrinsics.
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// RUN: %clang_cc1 -fcuda-is-device -triple nvptx-nvidia-cuda -S \
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// RUN: -disable-llvm-passes -o - %s \
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// RUN: | FileCheck -check-prefixes=COMMON,NV-ON %s
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// RUN: %clang_cc1 -fcuda-is-device -triple amdgcn-amd-amdhsa -S \
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// RUN: -target-cpu gfx906 -disable-llvm-passes -o - -x hip %s \
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// RUN: | FileCheck -check-prefixes=COMMON,AMD-ON %s
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// RUN: %clang_cc1 -fcuda-is-device -triple nvptx-nvidia-cuda -S \
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// RUN: -O3 -o - %s \
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// RUN: | FileCheck -check-prefixes=COMMON,NV-OPT-FAST %s
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// RUN: %clang_cc1 -fcuda-is-device -triple amdgcn-amd-amdhsa -S \
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// RUN: -O3 -target-cpu gfx906 -o - -x hip %s \
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// RUN: | FileCheck -check-prefixes=COMMON,AMD-OPT-FASTSTD %s
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// Check separate compile/backend steps corresponding to -save-temps.
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// RUN: %clang_cc1 -fcuda-is-device -triple amdgcn-amd-amdhsa -emit-llvm \
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// RUN: -O3 -disable-llvm-passes -target-cpu gfx906 -o %t.ll -x hip %s
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// RUN: cat %t.ll | FileCheck -check-prefixes=COMMON,AMD-OPT-FAST-IR %s
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// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -S \
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// RUN: -O3 -target-cpu gfx906 -o - -x ir %t.ll \
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// RUN: | FileCheck -check-prefixes=COMMON,AMD-OPT-FASTSTD %s
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// Explicit -ffp-contract=fast
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// In IR, fmul/fadd instructions with contract flag are emitted.
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// In backend
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// nvptx/amdgcn - assumes fast fp fuse option, which fuses
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// mult/add insts disregarding contract flag and
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// llvm.fmuladd intrinsics.
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// RUN: %clang_cc1 -fcuda-is-device -triple nvptx-nvidia-cuda -S \
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// RUN: -ffp-contract=fast -disable-llvm-passes -o - %s \
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// RUN: | FileCheck -check-prefixes=COMMON,NV-ON %s
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// RUN: %clang_cc1 -fcuda-is-device -triple amdgcn-amd-amdhsa -S \
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// RUN: -target-cpu gfx906 -disable-llvm-passes -o - -x hip %s \
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// RUN: -ffp-contract=fast \
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// RUN: | FileCheck -check-prefixes=COMMON,AMD-ON %s
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// RUN: %clang_cc1 -fcuda-is-device -triple nvptx-nvidia-cuda -S \
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// RUN: -O3 -o - %s \
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// RUN: -ffp-contract=fast \
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// RUN: | FileCheck -check-prefixes=COMMON,NV-OPT-FAST %s
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// RUN: %clang_cc1 -fcuda-is-device -triple amdgcn-amd-amdhsa -S \
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// RUN: -O3 -target-cpu gfx906 -o - -x hip %s \
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// RUN: -ffp-contract=fast \
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// RUN: | FileCheck -check-prefixes=COMMON,AMD-OPT-FAST %s
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// Check separate compile/backend steps corresponding to -save-temps.
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// When input is IR, -ffp-contract has no effect. Backend uses default
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// default FP fuse option.
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// RUN: %clang_cc1 -fcuda-is-device -triple amdgcn-amd-amdhsa -emit-llvm \
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// RUN: -ffp-contract=fast \
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// RUN: -O3 -disable-llvm-passes -target-cpu gfx906 -o %t.ll -x hip %s
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// RUN: cat %t.ll | FileCheck -check-prefixes=COMMON,AMD-OPT-FAST-IR %s
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// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -S \
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// RUN: -O3 -target-cpu gfx906 -o - -x ir %t.ll \
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// RUN: | FileCheck -check-prefixes=COMMON,AMD-OPT-FASTSTD %s
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// Explicit -ffp-contract=fast-honor-pragmas
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// In IR, fmul/fadd instructions with contract flag are emitted.
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// In backend
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// nvptx/amdgcn - assumes standard fp fuse option, which only
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// fuses mult/add insts with contract flag or
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// llvm.fmuladd intrinsics.
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// RUN: %clang_cc1 -fcuda-is-device -triple nvptx-nvidia-cuda -S \
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// RUN: -ffp-contract=fast-honor-pragmas -disable-llvm-passes -o - %s \
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// RUN: | FileCheck -check-prefixes=COMMON,NV-ON %s
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// RUN: %clang_cc1 -fcuda-is-device -triple amdgcn-amd-amdhsa -S \
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// RUN: -target-cpu gfx906 -disable-llvm-passes -o - -x hip %s \
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// RUN: -ffp-contract=fast-honor-pragmas \
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// RUN: | FileCheck -check-prefixes=COMMON,AMD-ON %s
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// RUN: %clang_cc1 -fcuda-is-device -triple nvptx-nvidia-cuda -S \
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// RUN: -O3 -o - %s \
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// RUN: -ffp-contract=fast-honor-pragmas \
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// RUN: | FileCheck -check-prefixes=COMMON,NV-OPT-FASTSTD %s
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// RUN: %clang_cc1 -fcuda-is-device -triple amdgcn-amd-amdhsa -S \
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// RUN: -O3 -target-cpu gfx906 -o - -x hip %s \
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// RUN: -ffp-contract=fast-honor-pragmas \
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// RUN: | FileCheck -check-prefixes=COMMON,AMD-OPT-FASTSTD %s
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// Check separate compile/backend steps corresponding to -save-temps.
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// When input is IR, -ffp-contract has no effect. Backend uses default
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// default FP fuse option.
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// RUN: %clang_cc1 -fcuda-is-device -triple amdgcn-amd-amdhsa -emit-llvm \
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// RUN: -ffp-contract=fast-honor-pragmas \
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// RUN: -O3 -disable-llvm-passes -target-cpu gfx906 -o %t.ll -x hip %s
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// RUN: cat %t.ll | FileCheck -check-prefixes=COMMON,AMD-OPT-FAST-IR %s
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// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -S \
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// RUN: -O3 -target-cpu gfx906 -o - -x ir %t.ll \
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// RUN: | FileCheck -check-prefixes=COMMON,AMD-OPT-FASTSTD %s
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// Explicit -ffp-contract=on -- fusing by front-end.
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// In IR,
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// mult/add in the same statement - llvm.fmuladd intrinsic emitted
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// mult/add in different statement - fmul/fadd instructions without
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// contract flag are emitted.
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// In backend
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// nvptx/amdgcn - assumes standard fp fuse option, which only
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// fuses mult/add insts with contract flag or
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// llvm.fmuladd intrinsics.
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// RUN: %clang_cc1 -fcuda-is-device -triple nvptx-nvidia-cuda -S \
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// RUN: -ffp-contract=on -disable-llvm-passes -o - %s \
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// RUN: | FileCheck -check-prefixes=COMMON,NV-ON %s
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// RUN: %clang_cc1 -fcuda-is-device -triple amdgcn-amd-amdhsa -S \
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// RUN: -target-cpu gfx906 -disable-llvm-passes -o - -x hip %s \
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// RUN: -ffp-contract=on \
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// RUN: | FileCheck -check-prefixes=COMMON,AMD-ON %s
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// RUN: %clang_cc1 -fcuda-is-device -triple nvptx-nvidia-cuda -S \
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// RUN: -O3 -o - %s \
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// RUN: -ffp-contract=on \
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// RUN: | FileCheck -check-prefixes=COMMON,NV-OPT-ON %s
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// RUN: %clang_cc1 -fcuda-is-device -triple amdgcn-amd-amdhsa -S \
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// RUN: -O3 -target-cpu gfx906 -o - -x hip %s \
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// RUN: -ffp-contract=on \
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// RUN: | FileCheck -check-prefixes=COMMON,AMD-OPT-ON %s
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// Check separate compile/backend steps corresponding to -save-temps.
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// RUN: %clang_cc1 -fcuda-is-device -triple amdgcn-amd-amdhsa -emit-llvm \
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// RUN: -ffp-contract=on \
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// RUN: -O3 -disable-llvm-passes -target-cpu gfx906 -o %t.ll -x hip %s
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// RUN: cat %t.ll | FileCheck -check-prefixes=COMMON,AMD-OPT-ON-IR %s
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// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -S \
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// RUN: -O3 -target-cpu gfx906 -o - -x ir %t.ll \
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// RUN: | FileCheck -check-prefixes=COMMON,AMD-OPT-ON %s
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// Explicit -ffp-contract=off should disable instruction fusing.
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// In IR, fmul/fadd instructions without contract flag are emitted.
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// In backend
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// nvptx/amdgcn - assumes standard fp fuse option, which only
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// fuses mult/add insts with contract flag or
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// llvm.fmuladd intrinsics.
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// RUN: %clang_cc1 -fcuda-is-device -triple nvptx-nvidia-cuda -S \
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// RUN: -ffp-contract=off -disable-llvm-passes -o - %s \
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// RUN: | FileCheck -check-prefixes=COMMON,NV-OFF %s
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// RUN: %clang_cc1 -fcuda-is-device -triple amdgcn-amd-amdhsa -S \
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// RUN: -target-cpu gfx906 -disable-llvm-passes -o - -x hip %s \
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// RUN: -ffp-contract=off \
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// RUN: | FileCheck -check-prefixes=COMMON,AMD-OFF %s
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// RUN: %clang_cc1 -fcuda-is-device -triple nvptx-nvidia-cuda -S \
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// RUN: -O3 -o - %s \
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// RUN: -ffp-contract=off \
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// RUN: | FileCheck -check-prefixes=COMMON,NV-OPT-OFF %s
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// RUN: %clang_cc1 -fcuda-is-device -triple amdgcn-amd-amdhsa -S \
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// RUN: -O3 -target-cpu gfx906 -o - -x hip %s \
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// RUN: -ffp-contract=off \
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// RUN: | FileCheck -check-prefixes=COMMON,AMD-OPT-OFF %s
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// Check separate compile/backend steps corresponding to -save-temps.
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// RUN: %clang_cc1 -fcuda-is-device -triple amdgcn-amd-amdhsa -emit-llvm \
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// RUN: -ffp-contract=off \
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// RUN: -O3 -disable-llvm-passes -target-cpu gfx906 -o %t.ll -x hip %s
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// RUN: cat %t.ll | FileCheck -check-prefixes=COMMON,AMD-OPT-OFF-IR %s
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// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -S \
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// RUN: -O3 -target-cpu gfx906 -o - -x ir %t.ll \
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// RUN: | FileCheck -check-prefixes=COMMON,AMD-OPT-OFF %s
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#include "Inputs/cuda.h"
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// Test multiply/add in the same statement, which can be emitted as FMA when
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// fp-contract is on or fast.
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__host__ __device__ float func(float a, float b, float c) { return a + b * c; }
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// COMMON-LABEL: _Z4funcfff
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// NV-ON: fma.rn.f32
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// NV-ON-NEXT: st.param.b32
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// AMD-ON: v_fmac_f32_e64
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// AMD-ON-NEXT: s_setpc_b64
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// NV-OFF: mul.rn.f32
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// NV-OFF-NEXT: add.rn.f32
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// NV-OFF-NEXT: st.param.b32
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// AMD-OFF: v_mul_f32_e64
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// AMD-OFF-NEXT: v_add_f32_e64
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// AMD-OFF-NEXT: s_setpc_b64
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// NV-OPT-FAST: fma.rn.f32
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// NV-OPT-FAST-NEXT: st.param.b32
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// NV-OPT-FASTSTD: fma.rn.f32
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// NV-OPT-FASTSTD-NEXT: st.param.b32
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// NV-OPT-ON: fma.rn.f32
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// NV-OPT-ON-NEXT: st.param.b32
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// NV-OPT-OFF: mul.rn.f32
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// NV-OPT-OFF-NEXT: add.rn.f32
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// NV-OPT-OFF-NEXT: st.param.b32
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// AMD-OPT-FAST-IR: fmul contract float
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// AMD-OPT-FAST-IR: fadd contract float
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// AMD-OPT-ON-IR: @llvm.fmuladd.f32
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// AMD-OPT-OFF-IR: fmul float
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// AMD-OPT-OFF-IR: fadd float
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// AMD-OPT-FAST: v_fmac_f32_e32
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// AMD-OPT-FAST-NEXT: s_setpc_b64
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// AMD-OPT-FASTSTD: v_fmac_f32_e32
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// AMD-OPT-FASTSTD-NEXT: s_setpc_b64
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// AMD-OPT-ON: v_fmac_f32_e32
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// AMD-OPT-ON-NEXT: s_setpc_b64
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// AMD-OPT-OFF: v_mul_f32_e32
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// AMD-OPT-OFF-NEXT: v_add_f32_e32
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// AMD-OPT-OFF-NEXT: s_setpc_b64
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// Test multiply/add in the different statements, which can be emitted as
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// FMA when fp-contract is fast but not on.
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__host__ __device__ float func2(float a, float b, float c) {
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float t = b * c;
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return t + a;
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}
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// COMMON-LABEL: _Z5func2fff
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// NV-OPT-FAST: fma.rn.f32
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// NV-OPT-FAST-NEXT: st.param.b32
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// NV-OPT-FASTSTD: fma.rn.f32
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// NV-OPT-FASTSTD-NEXT: st.param.b32
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// NV-OPT-ON: mul.rn.f32
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// NV-OPT-ON: add.rn.f32
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// NV-OPT-ON-NEXT: st.param.b32
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// NV-OPT-OFF: mul.rn.f32
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// NV-OPT-OFF: add.rn.f32
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// NV-OPT-OFF-NEXT: st.param.b32
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// AMD-OPT-FAST-IR: fmul contract float
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// AMD-OPT-FAST-IR: fadd contract float
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// AMD-OPT-ON-IR: fmul float
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// AMD-OPT-ON-IR: fadd float
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// AMD-OPT-OFF-IR: fmul float
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// AMD-OPT-OFF-IR: fadd float
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// AMD-OPT-FAST: v_fmac_f32_e32
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// AMD-OPT-FAST-NEXT: s_setpc_b64
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// AMD-OPT-FASTSTD: v_fmac_f32_e32
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// AMD-OPT-FASTSTD-NEXT: s_setpc_b64
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// AMD-OPT-ON: v_mul_f32_e32
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// AMD-OPT-ON-NEXT: v_add_f32_e32
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// AMD-OPT-ON-NEXT: s_setpc_b64
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// AMD-OPT-OFF: v_mul_f32_e32
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// AMD-OPT-OFF-NEXT: v_add_f32_e32
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// AMD-OPT-OFF-NEXT: s_setpc_b64
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// Test multiply/add in the different statements, which is forced
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// to be compiled with fp contract on. fmul/fadd without contract
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// flags are emitted in IR. In nvptx, they are emitted as FMA in
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// fp-contract is fast but not on, as nvptx backend uses the same
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// fp fuse option as front end, whereas fast fp fuse option in
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// backend fuses fadd/fmul disregarding contract flag. In amdgcn
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// they are not fused as amdgcn always use standard fp fusion
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// option which respects contract flag.
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__host__ __device__ float func3(float a, float b, float c) {
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#pragma clang fp contract(on)
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float t = b * c;
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return t + a;
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}
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// COMMON-LABEL: _Z5func3fff
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// NV-OPT-FAST: fma.rn.f32
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// NV-OPT-FAST-NEXT: st.param.b32
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// NV-OPT-FASTSTD: mul.rn.f32
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// NV-OPT-FASTSTD: add.rn.f32
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// NV-OPT-FASTSTD-NEXT: st.param.b32
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// NV-OPT-ON: mul.rn.f32
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// NV-OPT-ON: add.rn.f32
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// NV-OPT-ON-NEXT: st.param.b32
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// NV-OPT-OFF: mul.rn.f32
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// NV-OPT-OFF: add.rn.f32
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// NV-OPT-OFF-NEXT: st.param.b32
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// AMD-OPT-FAST-IR: fmul float
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// AMD-OPT-FAST-IR: fadd float
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// AMD-OPT-ON-IR: fmul float
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// AMD-OPT-ON-IR: fadd float
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// AMD-OPT-OFF-IR: fmul float
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// AMD-OPT-OFF-IR: fadd float
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// AMD-OPT-FAST: v_fmac_f32_e32
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// AMD-OPT-FAST-NEXT: s_setpc_b64
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// AMD-OPT-FASTSTD: v_mul_f32_e32
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// AMD-OPT-FASTSTD-NEXT: v_add_f32_e32
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// AMD-OPT-FASTSTD-NEXT: s_setpc_b64
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// AMD-OPT-ON: v_mul_f32_e32
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// AMD-OPT-ON-NEXT: v_add_f32_e32
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// AMD-OPT-ON-NEXT: s_setpc_b64
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// AMD-OPT-OFF: v_mul_f32_e32
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// AMD-OPT-OFF-NEXT: v_add_f32_e32
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// AMD-OPT-OFF-NEXT: s_setpc_b64
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