f3a674a2ef
Currently, AMDGPU functions have `target-features` attribute populated with all default features for the target GPU. This is redundant because the backend can derive these defaults from the `target-cpu` attribute via `AMDGPUTargetMachine::getFeatureString()`. In this PR, for AMDGPU targets only: - Functions without explicit target attributes no longer emit `target-features` - Functions with `__attribute__((target(...)))` or `-target-feature` emit only features that differ from the target's defaults (delta) The backend already handles missing `target-features` correctly by falling back to the TargetMachine's defaults. A new cc1 flag `-famdgpu-emit-full-target-features` is added to emit full features when needed. Example: Before: ```llvm attributes #0 = { "target-cpu"="gfx90a" "target-features"="+16-bit-insts,+atomic-buffer-global-pk-add-f16-insts,+atomic-fadd-rtn-insts,+ci-insts,+dl-insts,+dot1-insts,+dot2-insts,..." } ``` After (default): ```llvm attributes #0 = { "target-cpu"="gfx90a" } ``` After (with explicit `+wavefrontsize32` override): ```llvm attributes #0 = { "target-cpu"="gfx90a" "target-features"="+wavefrontsize32" } ```
48 lines
3.5 KiB
Common Lisp
48 lines
3.5 KiB
Common Lisp
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --check-attributes --check-globals all --include-generated-funcs --prefix-filecheck-ir-name VAR --version 6
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// RUN: %clang_cc1 -cl-std=CL2.0 -triple amdgcn-amd-amdhsa -target-cpu gfx1250 -disable-llvm-passes -fno-ident -emit-llvm %s -o - | FileCheck %s
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kernel void foo(global int *p) { *p = 1; }
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// CHECK: Function Attrs: convergent norecurse nounwind
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// CHECK-LABEL: define dso_local amdgpu_kernel void @foo(
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// CHECK-SAME: ptr addrspace(1) noundef align 4 [[P:%.*]]) #[[ATTR0:[0-9]+]] !kernel_arg_addr_space [[META7:![0-9]+]] !kernel_arg_access_qual [[META8:![0-9]+]] !kernel_arg_type [[META9:![0-9]+]] !kernel_arg_base_type [[META9]] !kernel_arg_type_qual [[META10:![0-9]+]] {
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// CHECK-NEXT: [[ENTRY:.*:]]
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// CHECK-NEXT: [[P_ADDR:%.*]] = alloca ptr addrspace(1), align 8, addrspace(5)
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// CHECK-NEXT: [[P_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[P_ADDR]] to ptr
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// CHECK-NEXT: store ptr addrspace(1) [[P]], ptr [[P_ADDR_ASCAST]], align 8, !tbaa [[INTPTR_TBAA11:![0-9]+]]
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// CHECK-NEXT: [[TMP0:%.*]] = load ptr addrspace(1), ptr [[P_ADDR_ASCAST]], align 8, !tbaa [[INTPTR_TBAA11]]
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// CHECK-NEXT: call void @__clang_ocl_kern_imp_foo(ptr addrspace(1) noundef align 4 [[TMP0]]) #[[ATTR2:[0-9]+]]
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// CHECK-NEXT: ret void
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//
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//
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// CHECK: Function Attrs: alwaysinline convergent norecurse nounwind
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// CHECK-LABEL: define dso_local void @__clang_ocl_kern_imp_foo(
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// CHECK-SAME: ptr addrspace(1) noundef align 4 [[P:%.*]]) #[[ATTR1:[0-9]+]] !kernel_arg_addr_space [[META7]] !kernel_arg_access_qual [[META8]] !kernel_arg_type [[META9]] !kernel_arg_base_type [[META9]] !kernel_arg_type_qual [[META10]] {
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// CHECK-NEXT: [[ENTRY:.*:]]
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// CHECK-NEXT: [[P_ADDR:%.*]] = alloca ptr addrspace(1), align 8, addrspace(5)
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// CHECK-NEXT: [[P_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[P_ADDR]] to ptr
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// CHECK-NEXT: store ptr addrspace(1) [[P]], ptr [[P_ADDR_ASCAST]], align 8, !tbaa [[INTPTR_TBAA11]]
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// CHECK-NEXT: [[TMP0:%.*]] = load ptr addrspace(1), ptr [[P_ADDR_ASCAST]], align 8, !tbaa [[INTPTR_TBAA11]]
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// CHECK-NEXT: store i32 1, ptr addrspace(1) [[TMP0]], align 4, !tbaa [[INT_TBAA3:![0-9]+]]
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// CHECK-NEXT: ret void
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//
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//.
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// CHECK: attributes #[[ATTR0]] = { convergent norecurse nounwind "amdgpu-cluster-dims"="0,0,0" "amdgpu-flat-work-group-size"="1,256" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="gfx1250" "uniform-work-group-size"="false" }
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// CHECK: attributes #[[ATTR1]] = { alwaysinline convergent norecurse nounwind "amdgpu-cluster-dims"="0,0,0" "amdgpu-flat-work-group-size"="1,256" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="gfx1250" }
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// CHECK: attributes #[[ATTR2]] = { convergent nounwind }
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//.
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// CHECK: [[META0:![0-9]+]] = !{i32 1, !"amdhsa_code_object_version", i32 600}
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// CHECK: [[META1:![0-9]+]] = !{i32 1, !"wchar_size", i32 4}
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// CHECK: [[META2:![0-9]+]] = !{i32 2, i32 0}
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// CHECK: [[INT_TBAA3]] = !{[[META4:![0-9]+]], [[META4]], i64 0}
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// CHECK: [[META4]] = !{!"int", [[META5:![0-9]+]], i64 0}
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// CHECK: [[META5]] = !{!"omnipotent char", [[META6:![0-9]+]], i64 0}
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// CHECK: [[META6]] = !{!"Simple C/C++ TBAA"}
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// CHECK: [[META7]] = !{i32 1}
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// CHECK: [[META8]] = !{!"none"}
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// CHECK: [[META9]] = !{!"int*"}
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// CHECK: [[META10]] = !{!""}
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// CHECK: [[INTPTR_TBAA11]] = !{[[META12:![0-9]+]], [[META12]], i64 0}
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// CHECK: [[META12]] = !{!"p1 int", [[META13:![0-9]+]], i64 0}
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// CHECK: [[META13]] = !{!"any pointer", [[META5]], i64 0}
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//.
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