44b94a4f75
This patch adds the target hooks required by Instruction Referencing for the AArch64 target, as mentioned in https://llvm.org/docs/InstrRefDebugInfo.html#target-hooks Which allows the Instruction Referenced LiveDebugValues Pass to track spills and restore instructions. With this patch we can use the `llvm/utils/llvm-locstats/llvm-locstats.py` to see the coverage statistics on a clang.dSYM built with in RelWithDebInfo we can see: coverage with dbg_value: ``` ================================================= Debug Location Statistics ================================================= cov% samples percentage(~) ------------------------------------------------- 0% 5828021 38% (0%,10%) 127739 0% [10%,20%) 143344 0% [20%,30%) 172100 1% [30%,40%) 193173 1% [40%,50%) 127366 0% [50%,60%) 308350 2% [60%,70%) 257055 1% [70%,80%) 212410 1% [80%,90%) 295316 1% [90%,100%) 349280 2% 100% 7313157 47% ================================================= -the number of debug variables processed: 15327311 -PC ranges covered: 67% ------------------------------------------------- -total availability: 62% ================================================= ``` coverage with InstrRef without target hooks fix: ``` ================================================= Debug Location Statistics ================================================= cov% samples percentage(~) ------------------------------------------------- 0% 6052807 39% (0%,10%) 127710 0% [10%,20%) 129999 0% [20%,30%) 155011 1% [30%,40%) 171206 1% [40%,50%) 102861 0% [50%,60%) 264734 1% [60%,70%) 212386 1% [70%,80%) 176872 1% [80%,90%) 242120 1% [90%,100%) 254465 1% 100% 7437215 48% ================================================= -the number of debug variables processed: 15327386 -PC ranges covered: 67% ------------------------------------------------- -total availability: 60% ================================================= ``` coverage with InstrRef with target hooks fix: ``` ================================================= Debug Location Statistics ================================================= cov% samples percentage(~) ------------------------------------------------- 0% 5972267 39% (0%,10%) 118873 0% [10%,20%) 127138 0% [20%,30%) 153181 1% [30%,40%) 170102 1% [40%,50%) 102180 0% [50%,60%) 263672 1% [60%,70%) 212865 1% [70%,80%) 176633 1% [80%,90%) 242403 1% [90%,100%) 264441 1% 100% 7494527 48% ================================================= -the number of debug variables processed: 15298282 -PC ranges covered: 71% ------------------------------------------------- -total availability: 61% ================================================= ``` I believe this should be a good indication that Instruction Referencing should be turned on for AArch64?
50 lines
1.4 KiB
LLVM
50 lines
1.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64-none-linux -O0 -tailcallopt < %s | FileCheck %s
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define void @bar() {
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; CHECK-LABEL: bar:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ret
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ret void
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}
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define fastcc i64 @foo(i64 %0, i64 %1, i64 %2, i64 %3, i64 %4, i64 %5, i64 %6, i64 %7, i64 %8) {
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; CHECK-LABEL: foo:
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; CHECK: // %bb.0:
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; CHECK-NEXT: add sp, sp, #16
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; CHECK-NEXT: ret
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ret i64 %0
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}
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; https://github.com/llvm/llvm-project/issues/60972
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define fastcc i64 @baz() {
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; CHECK-LABEL: baz:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: sub sp, sp, #32
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; CHECK-NEXT: str x30, [sp, #16] // 8-byte Spill
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; CHECK-NEXT: .cfi_def_cfa_offset 32
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; CHECK-NEXT: .cfi_offset w30, -16
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; CHECK-NEXT: mov x8, sp
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; CHECK-NEXT: mov x7, xzr
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; CHECK-NEXT: str xzr, [x8]
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; CHECK-NEXT: mov x0, x7
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; CHECK-NEXT: mov x1, x7
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; CHECK-NEXT: mov x2, x7
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; CHECK-NEXT: mov x3, x7
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; CHECK-NEXT: mov x4, x7
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; CHECK-NEXT: mov x5, x7
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; CHECK-NEXT: mov x6, x7
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; CHECK-NEXT: bl foo
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; CHECK-NEXT: sub sp, sp, #16
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; CHECK-NEXT: str x0, [sp, #8] // 8-byte Spill
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; CHECK-NEXT: bl bar
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; CHECK-NEXT: ldr x0, [sp, #8] // 8-byte Reload
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; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Reload
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; CHECK-NEXT: add sp, sp, #32
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; CHECK-NEXT: ret
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entry:
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%0 = tail call fastcc i64 @foo(i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0)
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call void @bar()
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ret i64 %0
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}
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